Difference between revisions of "Silicon Labs EFR32xG27"
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==Device Specific Handling== |
==Device Specific Handling== |
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===Reset=== |
===Reset=== |
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− | + | The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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− | ===Attach=== |
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− | * Attach is supported. |
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===Security=== |
===Security=== |
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+ | See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article. |
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− | * If device is secured, User is offered an unsecure by mass erase. |
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==Evaluation Boards== |
==Evaluation Boards== |
Revision as of 16:27, 10 October 2023
The Silicon Labs EFR32xG27 are wireless SoCs based on Cortex-M33 microcontrollers. These MCUs are part of the EFx32 Series 2 devices.
Sub families are:
- EFR32BG27
- EFR32MG27
Contents
EFx32 Series 2 specifics
Please refer to the Silicon Labs EFx32 Series 2 article.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal flash | 0x08000000 | 1024 KB | |
User Data | 0x0FE00000 | 1 KB |
Watchdog Handling
- The device has 1 Watchdog, which is fed during programming, if enabled.
Device Specific Handling
Reset
The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Security
See: Silicon Labs EFx32 Series 2 article.