This article describes specifics for the SiFive Arty FPGA Dev Kit.
Preparing for J-Link
Syntacore provides a reference FPGA bistream for the Digilent ARTY FPGA dev kit, which allows to implement a RISC-V core. The Digilent ARTY FPGA dev kit does not come with a standard debug connector but populates the debug JTAG signals on the JD connector of the eval board. Therefore, it needs to be manually wired in case J-Link shall be connected to it.
In the following, it is described how the pins of JD connector on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link.
|Pin JD (ARTY)||Pin J-Link||Description|
Note: The pins on the JD connector are numbered as follows:
Debugging in xxx
TBD Before continuing, make sure that you have J-Link software package Vxxx or later installed: Download J-Link software package
Minimum J-Link hardware requirements
Please note that RISC-V is not supported by older J-Link hardware models / revisions. For an overview about which models / revisions support RISC-V: List