Difference between revisions of "Syntacore SCR3"
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| − | The Syntacore SCR3 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip |
+ | The Syntacore SCR3 is a 32-bit (RV32) or 64-bit (RV64) core, designed by [https://syntacore.com/page/products/processor-ip Syntacore]. |
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= Requirements = |
= Requirements = |
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* A current J-Link model with RISC-V support |
* A current J-Link model with RISC-V support |
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| − | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.50b or later |
+ | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.50b or later (older versions will not work) |
| − | * The |
+ | * The SCR4 device selection is supported since V7.50b |
= RTT support = |
= RTT support = |
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= Limitations = |
= Limitations = |
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| − | * When debugging |
+ | * When debugging, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the core''' |
Revision as of 10:16, 15 February 2023
The Syntacore SCR3 is a 32-bit (RV32) or 64-bit (RV64) core, designed by Syntacore.
Requirements
- A current J-Link model with RISC-V support
- J-Link software V7.50b or later (older versions will not work)
- The SCR4 device selection is supported since V7.50b
RTT support
As the core does not support System Bus Access (SBA), RTT is not supported for this core.
HSS access
As the core does not support System Bus Access (SBA), HSS is not supported for this core.
Limitations
- When debugging, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the core
