TI Jacinto 7

The TI Jacinto 7 (TDA4 and DRA8) processors are are highly integrated processors designed for next-generation of ADAS and gateway applications

The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series.

General Information

There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface.

Device Specific Handling

Connect

No device specific initialization sequence is executed on connect. The J-Link SW assumes that the selected core is enabled / attach is possible.

Reset

In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a J-Link script file.

Multi-Core Support [OPTIONAL]

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The Jacinto 7 processors come with a variety of multi-core options.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

• Initializes the ECC RAM, see XXX
• Enables debugging

Reset

• Device specific reset is performed, see XXX

Attach

• Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

• If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
• If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed.

Attach

• Attach is supported / desired

Device Specific Handling

Reset

• The devices uses normal Cortex-M reset, no special handling necessary, like described here.
• The devices uses Cortex-M Core reset, no special handling necessary, like described here.
• The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
• The devices uses Cortex-A reset, no special handling necessary, like described here.
• The devices uses Cortex-R reset, no special handling necessary, like described here.
• The devices uses ARMv8-A reset, no special handling necessary, like described here.
• The devices uses ARMv8-R reset, no special handling necessary, like described here.
• The device uses custom reset:.....

Limitations

Dual Core Support

Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.

Attach

Attach is not supported by default because the J-Link initializes certain RAM regions by default.

Evaluation Boards

• [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard

Example Application

• [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project