Difference between revisions of "TI Jacinto 7"
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The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series. |
The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series. |
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==General Information== |
==General Information== |
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| − | There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface. |
+ | There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface. Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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===Reset=== |
===Reset=== |
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In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a [[J-Link_script_files | J-Link script file]]. |
In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a [[J-Link_script_files | J-Link script file]]. |
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| + | ==Supported Processors== |
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| + | === DRA821 === |
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| + | === TDA4VMx & DRA829Vx === |
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| − | == DRA821 == |
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| − | == TDA4VMx & DRA829Vx == |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The Jacinto 7 processors come with a variety of multi-core options.<br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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| − | |||
| − | ==Device Specific Handling== |
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| − | ===Connect=== |
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| − | ===Reset=== |
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| − | *The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The devices uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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| − | *The devices uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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| − | *The devices uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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| − | *The devices uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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| − | *The device uses custom reset:..... |
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| − | |||
| − | ==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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| − | ===Attach=== |
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| − | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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| − | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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Revision as of 12:43, 6 October 2023
The TI Jacinto 7 (TDA4 and DRA8) processors are are highly integrated processors designed for next-generation of ADAS and gateway applications
Contents
The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series.
General Information
There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface. Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
Device Specific Handling
Connect
No device specific initialization sequence is executed on connect. The J-Link SW assumes that the selected core is enabled / attach is possible.
Reset
In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a J-Link script file.
Supported Processors
DRA821
TDA4VMx & DRA829Vx
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
