Difference between revisions of "TI Jacinto 7"
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===Buffer tracing=== |
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Latest revision as of 14:42, 11 January 2024
The TI Jacinto 7 (TDA4 and DRA8) processors are are highly integrated processors designed for next-generation of ADAS and gateway applications
Contents
The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series.
General Information
There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface. Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
Device Specific Handling
Connect
No device specific initialization sequence is executed on connect. The J-Link SW assumes that the selected core is enabled / attach is possible.
Reset
In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a J-Link script file.
Supported Processors
DRA821
The following table provides an overview of which cores are supported:
| Core | J-Link support |
|---|---|
| MCU_R5_0 | 
|
| MCU_R5_1 |
|
| MAIN_R5_0_0 |
|
| MAIN_R5_0_1 |
|
| MAIN_A72_0 | 
|
| MAIN_A72_1 |
|
TDA4VMx & DRA829Vx
The following table provides an overview of which cores are supported:
| Core | J-Link support |
|---|---|
| MCU_R5_0 |
|
| MCU_R5_1 |
|
| MAIN_R5_0_0 |
|
| MAIN_R5_0_1 |
|
| MAIN_R5_1_0 |
|
| MAIN_R5_1_1 |
|
| MAIN_A72_0 |
|
| MAIN_A72_1 |
|
Evaluation Board
- TI Jacinto J721EXCP01EVM common evaluation platform: https://wiki.segger.com/TI_Jacinto_J721EXCP01EVM
- TI Jacinto J721EXSOMG01EVM system-on-module (TDA4VMx & DRA829Vx): https://wiki.segger.com/TI_Jacinto_J721EXCP01EVM
- TI Jacinto J7200XSOMG01EVM system-on-module (DRA821): https://wiki.segger.com/TI_Jacinto_J721EXCP01EVM
Instruction tracing
This section will provide information about what is needed to get instruction tracing going on the Jacinto 7 platform.
Note: Currently tracing only on the Cortex-R5 cores of this platform is supported.
Minimum requirements
- J-Link software V7.94c or later
- J-Trace Pro V3 or later
Example project
The following example project can be used with Ozone V3.30d or later and the TI Jacinto J721EXSOMG01EVM system-on-module (TDA4VMx & DRA829Vx). It will enable pin tracing on the R5_0 MCU core. The mainboard is labeled with PROC079E3 and the SoC board with PROC078A.
Project: TI_TDA4_DRA829_MCU_R5_0_TracePins.zip
How to launch the example project
- Insert the SD Card with the default Linux image that is shipped with the board mentioned above.
- Connect the UART debug port of the mainboard with your host pc. The Micro USB port is labeled J44.
- A green LED should light up now (LD11).
- Connect to the UART port on your host PC with some terminal software e.g. Putty or HTerm.
- The board will enumerate with 4 COM ports. Typically the one with the lowest number will have the console out later.
- Connection settings are 115200 Baud.
- Power your board via the power jack J7.
- If needed flip the power switch (SW2) to on.
- Let the Linux image boot through (takes up to 20 seconds).
- Boot is finished once the terminal halts and waits for an input.
- Connect your J-Trace Pro to connector J16, you will need a MIPI60 to Arm Cortex-M 20-Pin adapter.
- Makes sure the J-Trace Pro is powered and plugged in via USB3 to your host PC.
- Make sure all Ozone and the J-Link software are both installed.
- In the Linux console in your terminal program log is as root. (Username and password are both root for the default image).
- Execute the following commands in the Linux console:
- sudo i2cset -f -y 3 0x22 0x0d 0xf8
- sudo i2cset -f -y 3 0x22 0x05 0xff
- Now open the example project with Ozone (Ozone.jdebug file) and start the debug session.
If everything went right you should now see instruction trace coming from the target device.
Buffer tracing
Buffer tracing is available with J-Link software V7.94d and later. Due to a hardware limitation of the Jacinto 7 the trace buffer can only be operated in single shot fashion over short periods of time.
