TI Jacinto 7
The TI Jacinto 7 (TDA4 and DRA8) processors are are highly integrated processors designed for next-generation of ADAS and gateway applications
Contents
The Jacinto 7 platform features different processors with different features. From J-Link perspective, the main difference is the number of available cores. In the following, some generic information is given followed by the specific information for the DRA821 series as well as for the TDA4VM & DRA829Vx series.
General Information
There is a wide range of use cases in regard to the debug setup starting with debugging a bare-metal application development up to debugging an fully booted system (e.g. attaching). The J-Link implementation is targeting the latter use case thus assumes that there is already some kind of application (usually a Linux) running on the device which enables the desired core to be debugged. The J-Link performs a simple attach or download + attach. In latter case, the J-Link assumes that the MCU as well as the target address space (such as RAM) is (read / write) accessible via the debug interface. Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
Device Specific Handling
Connect
No device specific initialization sequence is executed on connect. The J-Link SW assumes that the selected core is enabled / attach is possible.
Reset
In multi-core based setups, reset of the secondary cores is usually very use case specific (e.g. reset selected core only; reset other cores / peripherals as well). The standard reset strategy for Cortex-A/R is based on a pin reset which would mess up the entire debug session. For that reason, the J-Link SW does not perform anything on reset. If a device specific reset handling is required, it needs to be implemented using a J-Link script file.
Supported Processors
DRA821
The following table provides an overview of which cores are supported:
| Core | J-Link support |
|---|---|
| MCU_R5_0 | 
|
| MCU_R5_1 |
|
| MAIN_R5_0_0 |
|
| MAIN_R5_0_1 |
|
| MAIN_R5_1_0 |
|
| MAIN_R5_1_1 |
|
| MAIN_A72_0 | 
|
| MAIN_A72_1 |
|
TDA4VMx & DRA829Vx
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
