Difference between revisions of "TMC"
(Created page with "The ARM CoreSight '''T'''race '''M'''emory '''C'''ontroller (TMC) supersedes the traditional ETM and ETB. It can be configured (at synthesization time of the device) t...") |
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| − | The ARM CoreSight '''T'''race '''M'''emory '''C'''ontroller (TMC) supersedes the traditional |
+ | The ARM CoreSight '''T'''race '''M'''emory '''C'''ontroller (TMC) supersedes the traditional [[ETB]]. |
It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. |
It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. |
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There are also some other configurations possible, but not really spread in the field right now and therefor not really used. |
There are also some other configurations possible, but not really spread in the field right now and therefor not really used. |
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Revision as of 14:49, 27 January 2021
The ARM CoreSight Trace Memory Controller (TMC) supersedes the traditional ETB. It can be configured (at synthesization time of the device) to act as a trace capture unit that outputs trace data on dedicated trace pins (similar to traditional ETM configuration) or as a trace capture unit that stores trace data in a RAM buffer. In contrast to traditional ETB, this buffer does not have to be on-chip RAM but may also be external high-speed RAM. There are also some other configurations possible, but not really spread in the field right now and therefor not really used.
