Difference between revisions of "Template:ST SR6Px MultiCoreSupport"
(Created page with "Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.<br> The {{{1}}} family comes with 6 C...") |
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The {{{1}}} family comes with |
+ | The {{{1}}} family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled ''lockstep'' mode, only.<br> |
Please refer to the reference manual. <br> |
Please refer to the reference manual. <br> |
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In below, the debug related multi-core behavior of the J-Link is described for each core:<br> |
In below, the debug related multi-core behavior of the J-Link is described for each core:<br> |
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===Cortex-R52 Cluster 0 Core 0 === |
===Cortex-R52 Cluster 0 Core 0 === |
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====Init/Setup==== |
====Init/Setup==== |
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| + | *WDT is enabled by default.<br> |
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| − | *Functional Reset is initiated for Cut 1.0 silicon. |
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| − | + | If it is enabled, it will be disabled. |
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====Reset==== |
====Reset==== |
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*Cortex-R Reset Pin is performed |
*Cortex-R Reset Pin is performed |
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| + | {{{2}}} |
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| − | *Functional Reset is initiated for Cut 1.0 silicon. |
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| − | *Initializes the |
+ | *Initializes the 256KB ECC RAM starting at 0x60000000 |
| − | *WDT is |
+ | *WDT is enabled by default.<br> |
| + | If it is enabled, it will be disabled. |
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====Attach==== |
====Attach==== |
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| − | *Attach is supported, user has to take care about ECC RAM |
+ | *Attach is supported, user has to take care about ECC RAM initialization. |
===Cortex-R52 Cluster 0 Core 1 === |
===Cortex-R52 Cluster 0 Core 1 === |
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Revision as of 12:21, 7 August 2023
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The {{{1}}} family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Contents
Cortex-R52 Cluster 0 Core 0
Init/Setup
- WDT is enabled by default.
If it is enabled, it will be disabled.
Reset
- Cortex-R Reset Pin is performed
{{{2}}}
- Initializes the 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default.
If it is enabled, it will be disabled.
Attach
- Attach is supported, user has to take care about ECC RAM initialization.
Cortex-R52 Cluster 0 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 2 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
DSPH Core
Init/Setup
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
