Difference between revisions of "Template:ST SR6Px MultiCoreSupport"
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(→Reset) |
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*WDT is enabled by default. If it is enabled, it will be disabled. |
*WDT is enabled by default. If it is enabled, it will be disabled. |
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====Reset==== |
====Reset==== |
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| − | *ARMv8-R Reset is performed like described[[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]] |
+ | *ARMv8-R Reset is performed like described [[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]]. |
{{{2}}} |
{{{2}}} |
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| − | *Initializes |
+ | *Initializes 256KB ECC RAM starting at 0x60000000 |
*WDT is enabled by default. If it is enabled, it will be disabled. |
*WDT is enabled by default. If it is enabled, it will be disabled. |
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| Line 20: | Line 20: | ||
*If core is not enabled, it will be enabled (set to DRUN condition). |
*If core is not enabled, it will be enabled (set to DRUN condition). |
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====Reset==== |
====Reset==== |
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| + | *ARMv8-R Reset is performed like described [[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]]. |
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| − | *Cortex-R Reset Pin is performed |
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====Attach==== |
====Attach==== |
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*Attach is supported |
*Attach is supported |
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| Line 29: | Line 29: | ||
*If core is not enabled, it will be enabled (set to DRUN condition). |
*If core is not enabled, it will be enabled (set to DRUN condition). |
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====Reset==== |
====Reset==== |
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| + | *ARMv8-R Reset is performed like described [[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]]. |
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| − | *Cortex-R Reset Pin is performed |
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====Attach==== |
====Attach==== |
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*Attach is supported |
*Attach is supported |
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| Line 38: | Line 38: | ||
*If core is not enabled, it will be enabled (set to DRUN condition). |
*If core is not enabled, it will be enabled (set to DRUN condition). |
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====Reset==== |
====Reset==== |
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| + | *ARMv8-R Reset is performed like described [[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]]. |
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| − | *Cortex-R Reset Pin is performed |
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====Attach==== |
====Attach==== |
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*Attach is supported |
*Attach is supported |
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| Line 47: | Line 47: | ||
*If core is not enabled, it will be enabled (set to DRUN condition). |
*If core is not enabled, it will be enabled (set to DRUN condition). |
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====Reset==== |
====Reset==== |
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| + | *ARMv8-R Reset is performed like described [[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]]. |
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| − | *Cortex-R Reset Pin is performed |
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====Attach==== |
====Attach==== |
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*Attach is supported |
*Attach is supported |
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===DSPH Core === |
===DSPH Core === |
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====Init/Setup==== |
====Init/Setup==== |
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| + | * none |
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| − | * |
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| + | |||
====Reset==== |
====Reset==== |
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| − | *Cortex- |
+ | *Cortex-M Typ 0 normal reset is performed like described [[J-Link_Reset_Strategies#Type_0:_Normal|here]]. |
| + | |||
| + | ====Attach==== |
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| + | *Attach is supported |
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| + | |||
| + | ===DME Core === |
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| + | ====Init/Setup==== |
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| + | * none |
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| + | |||
| + | ====Reset==== |
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| + | *Cortex-M Typ 0 normal reset is performed like described [[J-Link_Reset_Strategies#Type_0:_Normal|here]]. |
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| + | |||
====Attach==== |
====Attach==== |
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*Attach is supported |
*Attach is supported |
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Latest revision as of 15:28, 7 August 2023
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The {{{1}}} family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Contents
Cortex-R52 Cluster 0 Core 0
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
Reset
- ARMv8-R Reset is performed like described here.
{{{2}}}
- Initializes 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default. If it is enabled, it will be disabled.
Attach
- Attach is supported, user has to take care about ECC RAM initialization.
Cortex-R52 Cluster 0 Core 1
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 2 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
DSPH Core
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
DME Core
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
