Template:ST SR6Px MultiCoreSupport

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The {{{1}}} family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-R52 Cluster 0 Core 0

Init/Setup

• WDT is enabled by default. If it is enabled, it will be disabled.

Reset

• ARMv8-R Reset is performed like described[J-Link_Reset_Strategies#Strategies_for_ARMv8-R_devices|here]

{{{2}}}

• Initializes the 256KB ECC RAM starting at 0x60000000
• WDT is enabled by default. If it is enabled, it will be disabled.

Attach

• Attach is supported, user has to take care about ECC RAM initialization.

Cortex-R52 Cluster 0 Core 1

Init/Setup

• WDT is enabled by default. If it is enabled, it will be disabled.
• If core is not enabled, it will be enabled (set to DRUN condition).

Reset

• Cortex-R Reset Pin is performed

Attach

• Attach is supported

Cortex-R52 Cluster 1 Core 0

Init/Setup

• WDT is disabled
• If core is not enabled, it will be enabled (set to DRUN condition).

Reset

• Cortex-R Reset Pin is performed

Attach

• Attach is supported

Cortex-R52 Cluster 1 Core 1

Init/Setup

• WDT is disabled
• If core is not enabled, it will be enabled (set to DRUN condition).

Reset

• Cortex-R Reset Pin is performed

Attach

• Attach is supported

Cortex-R52 Cluster 2 Core 0

Init/Setup

• WDT is disabled
• If core is not enabled, it will be enabled (set to DRUN condition).

Reset

• Cortex-R Reset Pin is performed

Attach

• Attach is supported

DSPH Core

Reset

• Cortex-R Reset Pin is performed

Attach

• Attach is supported