Difference between revisions of "Tracing on Infineon Traveo II (CYT4BF)"
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For source templates we recommend to get in contact with Infineon support directly. |
For source templates we recommend to get in contact with Infineon support directly. |
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− | + | {{Note|1= The publicly available reference manual for this device does not show the trace funnel bits correctly. Correct would be as follows: Bit0 and Bit1 are connected to the ITM and ETM of the M7_0 core. Bit2 and Bit3 are connected to the ITM and ETM of the M7_1 core.}} |
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=== Cortex-M0+ Core === |
=== Cortex-M0+ Core === |
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This board does not have trace pins connected to the debug header by default. Please refer to the Infineon board manual for information about how to connect the pins. |
This board does not have trace pins connected to the debug header by default. Please refer to the Infineon board manual for information about how to connect the pins. |
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+ | ===== Trace clock signal quality ===== |
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+ | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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+ | [[File:230413_Multiple_Tclk.png|none|thumb|Trace clock signal quality]] |
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+ | ===== Rise time ===== |
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+ | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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+ | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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+ | [[File:230413_Risetime_tclk.png|none|thumb|TCLK rise time]] |
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+ | ===== Setup time ===== |
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+ | The setup time shows the relative setup time between a trace data signal and trace clock. |
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+ | The measurement markers are set at 50% of the expected voltage level respectively. |
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+ | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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+ | [[File:230413_SetupTime_td0.png|none|thumb|TD0 setup time]] |
Latest revision as of 14:50, 13 April 2023
Contents
This article describes how to get started with trace on the Infineon Traveo II (CYT4BF) MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Infineon Traveo II (CYT4BF) MCU implements tracing via pins, so a J-Trace can be used for tracing.
Minimum requirements
In order to use trace on the Infineon Traveo II (CYT4BF) MCU devices, the following minimum requirements have to be met:
- J-Link software version V7.82b or later
- Ozone V3.24c or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V2.0 or later
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Sample projects
The following sample projects are designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The projects have been tested with the minimum requirements mentioned above and a CYTVII-B-H-8M-320-CPU eval board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
The Infineon CYT4BF is a triple core device with dual Cortex-M7 and a Cortex-M0+ which have different trace capabilities.
Cortex-M7_0 Core
Streaming Trace: Infineon_CYT4BF_CM7_0_TracePins.zip
Buffer Trace: Infineon_CYT4BF_CM7_0_TraceBuffer.zip
Cortex-M7_1 Core
The second M7 core is unfortunately not able to access the shared trace registers directly so the complete Arm coresight and board specific trace pin and clock init must be executed via an application running inside the first M7 core. For source templates we recommend to get in contact with Infineon support directly.
The publicly available reference manual for this device does not show the trace funnel bits correctly. Correct would be as follows: Bit0 and Bit1 are connected to the ITM and ETM of the M7_0 core. Bit2 and Bit3 are connected to the ITM and ETM of the M7_1 core.
Cortex-M0+ Core
Buffer Trace: Infineon_CYT4BF_CM0_TraceBuffer.zip
Some examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
You can also create your own JLink Script file. How is explained here: How_to_configure_JLinkScript_files_to_enable_tracingTested Hardware
This board does not have trace pins connected to the debug header by default. Please refer to the Infineon board manual for information about how to connect the pins.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.