Tracing on Infineon Traveo II (CYT4BF)

This article describes how to get started with trace on the Infineon Traveo II (CYT4BF) MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Infineon Traveo II (CYT4BF) MCU implements tracing via pins, so a J-Trace can be used for tracing.

Minimum requirements

In order to use trace on the Infineon Traveo II (CYT4BF) MCU devices, the following minimum requirements have to be met:

• J-Link software version V7.82b or later
• Ozone V3.24c or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V2.0 or later

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Sample projects

The following sample projects are designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The projects have been tested with the minimum requirements mentioned above and a CYTVII-B-H-8M-320-CPU eval board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.

The Infineon CYT4BF is a triple core device with dual Cortex-M7 and a Cortex-M0+ which have different trace capabilities.

Cortex-M7_0 Core

Streaming Trace: Infineon_CYT4BF_CM7_0_TracePins.zip

Buffer Trace: Infineon_CYT4BF_CM7_0_TraceBuffer.zip

Cortex-M7_1 Core

TBD

Cortex-M0+ Core

Buffer Trace: Infineon_CYT4BF_CM0_TraceBuffer.zip

Note:

Some examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

You can also create your own JLink Script file. How is explained here: How_to_configure_JLinkScript_files_to_enable_tracing

Tested Hardware

CYTVII-B-H-8M-320-CPU

Note:
This board does not have trace pins connected to the debug header by default. Please refer to the Infineon board manual for information about how to connect the pins.