Difference between revisions of "Tracing on Infineon XMC4500 series MCUs"
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| − | This article describes how to add support for new devices / flash banks to the J-Link DLL so that they can be used with any J-Link DLL based application like for example J-Flash, J-Link Commander, IDEs, etc...This article assumes that there is already a basic understanding of the method of adding new devices using the Open Flashloader concept. If this is not the case, we recommend to read the '''Open Flashloader''' chapter in the J-Link User Manual (UM08001). In general, there are two possibilities to add support for a new device: |
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| − | #'''Use a pre-compiled flash loader''' |
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| − | #'''Compile / create the flash loader on your own''' |
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| − | ##Using Keil uVision (a license is required, no trial available; Supports Cortex-M, only) |
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| − | ##SEGGER Embedded Studio (can be evaluated without license; Supports Cortex-M and Cortex-A/R)<br>How to create a flash loader on your own using Embedded Studio is described below. |
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| − | = Creating a flash algorithm using SEGGER Embedded Studio = |
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| − | This article describes how to create a flash loader using the template projects (Cortex-M and Cortex-A/R) for SEGGER Embedded Studio. |
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| − | == Debug Configurations == |
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| − | The example project contains two debug configurations: |
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| − | *Debug |
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| − | *Release |
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| − | === Debug configuration === |
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| − | This configuration allows to debug the flash algorithm in Embedded Studio. The configuration includes a main.c containing the typical function call order, executed by the J-Link DLL during flash programming. The optimization level for this configuration is set to "none". |
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| − | === Release configuration === |
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| − | This configuration does not allow debugging but creates the output elf file which can be referenced from within the JLinkDevices.xml file as "''Loader''". The optimization level is set to 3 (highest). |
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| − | == Included files == |
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| − | {| class="wikitable" |
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| − | |- |
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| − | ! Filename !! Content |
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| − | |- |
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| − | | '''FlashDev.c''' || Flash device description for the ST STM32F205RC |
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| − | |- |
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| − | | '''FlashOS.h''' || Function prototypes, definitions and structures |
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| − | |- |
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| − | | '''FlashPrg.c''' || Flash algorithm itself (e.g. ProgramPage(), EraseSector() |
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| − | |- |
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| − | | '''main.c''' || Flash algorithm debug code (used by debug configuration, only) |
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| − | |- |
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| − | | '''Cortex_M_Startup.s'''<br>'''ARM_Startup.s''' || Cortex-M startup code (used by debug configuration, only) <br> Cortex-A/R startup code (used by debug configuration, only) |
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| − | |- |
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| − | | '''MemoryMap.xml''' || Memory map of the ST STM32F205RC |
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| − | |- |
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| − | | '''Placement_debug.xml''' || Debug configuration section placement file. |
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| − | |- |
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| − | | '''Placement_release.xml''' || Release configuration section placement file. |
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| − | |- |
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| − | | '''thumb_crt0.s'''<br>'''crt0.s''' || Initialization file for Cortex-M (used by debug configuration, only)<br>Initialization file for Cortex-A/R(used by debug configuration, only) |
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| − | |} |
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| − | == Embedded Studio Template Projects == |
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| − | The template projects below have been tested with SEGGER Embedded Studio V3.10. |
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| − | *[[File:OpenFlashLoader_CortexM_Template_EmbeddedStudio.zip]] |
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| − | *[[File:OpenFlashLoader_CortexAR_Template_EmbeddedStudio.zip]] |
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| + | This article describes how to get started with trace on the Infineon XMC4500 series. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
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| − | == Step-By-Step Instruction == |
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| + | The Infineon XMC4500 series implements tracing via pins only, so a J-Trace is needed to perform tracing on these devices. |
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| − | This step-by-step instruction explains how to create your own flash loader using the template projects for Embedded Studio and how to use add a new flash bank for an existing or new device to the J-Link DLL, so that it can be used from within any application using the DLL. |
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| − | #Adapt the template project |
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| − | ##'''FlashDev.c''': Modify the FlashDevice structure according to your device |
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| − | ##'''FlashPrg.c''': Implement the flash routines Init(), UnInit(), EraseSector() and ProgramPage() |
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| − | ##'''MemoryMap.xml''': Enter RAM base address and RAM size |
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| − | ##'''main.c''': Make sure that the define ''_FLASH_BASE_ADDR'' defines the correct flash base address |
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| − | #Test the debug configuration |
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| − | ##Connect the target to the J-Link and the J-Link to the PC |
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| − | ##Switch to the '''Debug''' configuration in Embedded Studio ('''Build''' -> '''Set Active Build Configuration''' -> '''Debug''') |
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| − | ##Build the project by pressing '''F7''' |
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| − | ##Start the debug session by pressing '''F5''' |
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| − | ##PC should be halted at main. Now debug the flash algorithm and make sure that it behaves as expected. |
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| − | #Build the flash loader using the release configuration |
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| − | ##Switch to the '''Release''' configuration in Embedded Studio ('''Build''' -> '''Set Active Build Configuration''' -> '''Release''') |
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| − | ##Build the project by pressing '''F7''' --> The flash loader file can be found here: $PROJ_DIR$\Output\Release\Exe\*.elf |
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| − | #JLinkDevices.xml |
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| − | ##Create or adapt the '''JLinkDevices.xml''' (described in the J-Link User Manual (UM08001)). |
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| − | ##Place the '''JLinkDevices.xml''' file at the correct location (described in the J-Link User Manual (UM08001)). |
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| − | Now you can select and use the created or adapted device which uses the new flash bank in any J-Link DLL based application (e.g. J-Link Commander / IDE / ...). |
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| − | == Frequently Asked Questions == |
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| − | In which order does the J-Link DLL call the function during flash programming? |
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| − | #Compare |
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| − | ##Init() |
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| − | ##Compare()<br>Memory is accessed so it has to be initialized during Init() so that it can be memory mapped accessed here. If it is not initialized correctly, the read access may results in confusing the MCU. |
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| − | ##UnInit() |
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| − | # Erase |
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| − | ## Init() |
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| − | ## Erase() |
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| − | ## UnInit() |
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| − | # Program |
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| − | ## Init() |
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| − | ## Program() |
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| − | ## UnInit() |
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| − | == Troubleshoot == |
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| − | This section provides assistance in case of issues pops up when using custom added flash bank. The section assumes that the functionality has been verified using the debug configuration in Embedded Studio. |
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| − | #Get the latest version of the template project |
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| − | #Follow the Step-By-Step instructions expect of 2.1 FlashPrg.c --> Functions should not contain any code that accesses any SFRs |
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| − | #Build the flash loader using the release configuration |
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| − | #Perform a flash download using J-Link Commander. Flash download should report an error during verify |
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| − | #Implement EraseSector() and retry the flash download test. J-Link Commander should still report verify failed but effected flash memory region should be empty. If not, check EraseSector(). |
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| − | #Implement ProgramPage() and retry the flash download test. Expected result: Test reports O.K. --> Programmed successfully. If not, check ProgramPage() code. |
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| − | == |
+ | == Minimum requirements == |
| + | In order to use trace on the Infineon XMC4500 series devices, the following minimum requirements have to be met: |
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| − | === PC has unexpected value after flash download === |
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| + | * J-Link software version V6.18c or later |
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| − | This error may have different root causes: |
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| + | * Ozone V2.46a or later (if streaming trace and / or the sample project from below shall be used) |
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| − | *Watchdog is enabled but not fed in the flash loader functions. This may result in a watchdog timeout pops up during RAMCode execution. The behavior is different but usually a reset will be triggered. |
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| + | * J-Trace PRO for Cortex-M HW version V1.0 or later |
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| − | *Accessing not enabled / clocked special function registers / peripherals |
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| + | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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| − | *Accessing invalid memory regions (reserved) |
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| + | |||
| − | ===(Q)SPI flashes=== |
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| + | == Sample project == |
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| − | *The Init() code has to make sure that the (Q)SPI pins as well as the (Q)SPI controller are configured so that the flash can be memory mapped (read) accessed. This is necessary as the J-Link DLL reads the data before programming to check if flash content does already match. This can be validated by setting the compare method in J-Link Commander to "skip" (exec SetCompareMode 0). Now start flash download. J-Link Commander should report a verify error but the flash should be memmory mapped accessible from now. If not, check the Init() code. |
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| + | The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above on a XMC4500_CPU_45A-V3 Kit (Hexagon Board). The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. But the examples are all pre-build and work out-of-the box with Ozone, so rebuilding is not necessary. |
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| + | |||
| + | [[Media:Infineon XMC4500-1024 CPU 45A-V3 120MHz TraceExample pex.zip | Infineon XMC4500-1024 CPU 45A-V3 120MHz TraceExample.zip]] |
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| + | |||
| + | {{Note|The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.<br> |
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| + | |||
| + | To create your own .JLinkScriptfile you can use the following guide as reference: [[How_to_configure_JLinkScript_files_to_enable_tracing]] |
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| + | |||
| + | }} |
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| + | |||
| + | == Tested Hardware == |
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| + | [[File:Infineon_XMC4500_CPU_45A-V3_Kit.jpg|none|thumb|XMC4500_CPU_45A-V3 Kit (Hexagon Board)]] |
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| + | |||
| + | == Reference trace signal quality == |
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| + | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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| + | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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| + | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| + | === Rise time === |
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| + | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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| + | [[File:XMC4500_TCLK_Risetime.png|none|thumb|TCLK rise time]] |
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| + | === Setup time === |
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| + | The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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| + | [[File:XMC4500_TD0_Setuptime.png|none|thumb|TD0 setup time]] |
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Latest revision as of 14:32, 15 August 2023
Contents
This article describes how to get started with trace on the Infineon XMC4500 series. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Infineon XMC4500 series implements tracing via pins only, so a J-Trace is needed to perform tracing on these devices.
Minimum requirements
In order to use trace on the Infineon XMC4500 series devices, the following minimum requirements have to be met:
- J-Link software version V6.18c or later
- Ozone V2.46a or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Sample project
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above on a XMC4500_CPU_45A-V3 Kit (Hexagon Board). The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used. But the examples are all pre-build and work out-of-the box with Ozone, so rebuilding is not necessary.
Infineon XMC4500-1024 CPU 45A-V3 120MHz TraceExample.zip
Note:
The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
