Difference between revisions of "e-peas EDMS105N"
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| − | The '''e-peas EDMS105N''' are |
+ | The '''e-peas EDMS105N''' are extremely Low-Power Microcontrollers based on Cortex-M0. |
__TOC__ |
__TOC__ |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | |
+ | | Main Flash || 0x00000000 || 256 KB || style="text-align:center;"| {{YES}} |
| − | |} |
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| − | |||
| − | ====ECC Flash [OPTIONAL]==== |
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| − | *Describe ECC Flash restriction here. |
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| − | |||
| − | ===QSPI Flash=== |
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| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| − | {| class="seggertable" |
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|- |
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| + | | Info Flash || 0x01000000 || 2 KB || style="text-align:center;"| {{YES}} |
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| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| − | |- |
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| − | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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| − | *'''[LOADER_NAME]''' |
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| − | *[LOADER_NAME] |
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| − | *[LOADER_NAME] |
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|} |
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| − | |||
| − | ==ECC RAM [OPTIONAL]== |
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| − | *Describe ECC RAM restriction here. |
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| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
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| − | *Describe Vector Table Remap here.. |
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==Watchdog Handling== |
==Watchdog Handling== |
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| − | *The device |
+ | *The device has a watchdog WDT. |
| − | *The device has a watchdog [WATCHDOGNAME]. |
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*The watchdog is fed during flash programming. |
*The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| + | ==Device Specific Handling== |
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| + | ===Info Flash=== |
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| + | The EDMS105N has a key storage (0x01000000 to 0x0100007F) at the beginning of the Info Flash sector (0x01000000 to 0x010000800) which is NOT readable, only writable.<br> |
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| + | Any readout of the key storage (0x01000000 to 0x0100007F), will show up 0xFF, instead of the programmed values.<br> |
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| + | *User can read the whole Info sector (keys are displayed as 0xFF, even if they are programmed).<br> |
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| + | *User can verify the programmed data (when no keys are programmed).<br> |
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| + | *When user programs data into the Info Flash sector with keys included, verify has to be switched off, or it will fail.<br> |
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| + | ==Reset== |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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| − | |||
| − | ==Device Specific Handling== |
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| − | ===Connect=== |
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| − | ===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The device uses custom reset:..... |
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| − | == |
+ | ==Unsecure== |
| + | If J-Link detects any write protected flash page (MAINLOCK) or a fully protected device (DBGLOCK) the user is offered a chip erase before connecting to the device. |
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| − | ===Dual Core Support=== |
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| + | At the moment the INFOLOCK can't be reset. |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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| − | ===Attach=== |
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| − | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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| − | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | * |
+ | *e-peas EDMS105N_EVK evaluation board: https://wiki.segger.com/e-peas_EDMS105N_EVK |
==Example Application== |
==Example Application== |
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| − | * |
+ | *e-peas EDMS105N_EVK evaluation board: https://wiki.segger.com/e-peas_EDMS105N_EVK#Example_Project |
Revision as of 07:59, 13 July 2023
The e-peas EDMS105N are extremely Low-Power Microcontrollers based on Cortex-M0.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main Flash | 0x00000000 | 256 KB | 
|
| Info Flash | 0x01000000 | 2 KB |
|
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog is fed during flash programming.
Device Specific Handling
Info Flash
The EDMS105N has a key storage (0x01000000 to 0x0100007F) at the beginning of the Info Flash sector (0x01000000 to 0x010000800) which is NOT readable, only writable.
Any readout of the key storage (0x01000000 to 0x0100007F), will show up 0xFF, instead of the programmed values.
- User can read the whole Info sector (keys are displayed as 0xFF, even if they are programmed).
- User can verify the programmed data (when no keys are programmed).
- When user programs data into the Info Flash sector with keys included, verify has to be switched off, or it will fail.
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Unsecure
If J-Link detects any write protected flash page (MAINLOCK) or a fully protected device (DBGLOCK) the user is offered a chip erase before connecting to the device. At the moment the INFOLOCK can't be reset.
Evaluation Boards
- e-peas EDMS105N_EVK evaluation board: https://wiki.segger.com/e-peas_EDMS105N_EVK
Example Application
- e-peas EDMS105N_EVK evaluation board: https://wiki.segger.com/e-peas_EDMS105N_EVK#Example_Project
