Difference between revisions of "embOS MPU on CortexM"
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== FAQ == |
== FAQ == |
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− | '''I want use the Cortex-M memory attributes with embOS-MPU Cortex-M |
+ | '''I want use the Cortex-M memory attributes with embOS-MPU Cortex-M''' |
The Cortex-M memory attributes include the following: |
The Cortex-M memory attributes include the following: |
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− | Bufferable: |
+ | '''Bufferable:''' |
Write to memory can be carried out by a write buffer while the processor continues on next instruction execution. |
Write to memory can be carried out by a write buffer while the processor continues on next instruction execution. |
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− | Cacheable: |
+ | '''Cacheable:''' |
Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution. |
Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution. |
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− | Sharable: |
+ | '''Sharable:''' |
Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region. |
Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region. |
Revision as of 17:18, 13 May 2019
embOS is a priority-controlled real-time operating system, designed to be used as foundation for the development of embedded applications.
FAQ
I want use the Cortex-M memory attributes with embOS-MPU Cortex-M
The Cortex-M memory attributes include the following:
Bufferable: Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
Cacheable: Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
Sharable: Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.