Difference between revisions of "embOS MPU on CortexM"
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With embOS-MPU Cortex-M the ''Attribute'' parameter is shifted by 16 bits and set in the Coretx-M Region Base Attribute and Size Register. |
With embOS-MPU Cortex-M the ''Attribute'' parameter is shifted by 16 bits and set in the Coretx-M Region Base Attribute and Size Register. |
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+ | Example: |
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+ | <nowiki> |
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+ | Setting the Cacheable and Bufferable of a memory region: |
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+ | |||
+ | #define BUFFERABLE (1u << 0) |
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+ | #define CACHEABLE (1u << 1) |
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+ | |||
+ | OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, BUFFERABLE | CACHEABLE); |
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+ | |||
+ | </nowiki> |
Revision as of 17:37, 13 May 2019
embOS is a priority-controlled real-time operating system, designed to be used as foundation for the development of embedded applications.
FAQ
I want use the Cortex-M memory attributes with embOS-MPU Cortex-M
The Cortex-M memory attributes include the following:
Bufferable: Write to memory can be carried out by a write buffer while the processor continues on next instruction execution.
Cacheable: Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up the program execution.
Sharable: Data in this memory region could be shared by multiple bus masters. Memory system needs to ensure coherency of data between different bus masters in shareable memory region.
TEX: Type Extension field
These bits are implemented in the Cortex-M MPU Region Base Attribute and Size Register (0xE000EDA0):
31:29 Reserved 28 XN R/W — Instruction Access Disable (1 = disable instruction fetch from this region; an attempt to do so will result in a memory management fault) 27 Reserved 26:24 AP R/W — Data Access Permission field 23:22 Reserved 21:19 TEX R/W — Type Extension field 18 S R/W — Shareable 17 C R/W — Cacheable 16 B R/W — Bufferable 15:8 SRD R/W — Subregion disable 7:6 Reserved 5:1 REGION SIZE R/W — MPU Protection Region size 0 ENABLE R/W — Region enable
Encoding of Inner and Outer Cache Policy When Most Significant Bit of TEX Is Set to 1
Memory Attribute Encoding (AA and BB) Cache Policy 00 Noncacheable 01 Write back, write, and read allocate 10 Write through, no write allocate 11 Write back, no write allocate
OS_MPU_AddRegion() prototype:
void OS_MPU_AddRegion(OS_TASK* pTask, OS_U32 BaseAddr, OS_U32 Size, OS_U32 Permissions, OS_U32 Attributes);
With embOS-MPU Cortex-M the Attribute parameter is shifted by 16 bits and set in the Coretx-M Region Base Attribute and Size Register. Example:
Setting the Cacheable and Bufferable of a memory region: #define BUFFERABLE (1u << 0) #define CACHEABLE (1u << 1) OS_MPU_AddRegion(&HPTask, 0x00, 0x2000, OS_MPU_READONLY, BUFFERABLE | CACHEABLE);