Cyclone V series
The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores.
J-Link supports debugging both Cortex-A9 cores of the Cyclone V. What is needed is one instance of the IDE (SEGGER Ozone, Eclipse + GDBServer, ...) per core to be debugged. Intel describes the cores as follows in their manual:
CPU0 => Core 0 which is the default core from which the device boots. It is available after reset CPU1 => Core 1 which needs to be enabled/released from reset by the application running on core 0
Connecting to core 0
Connecting to core 0 (default core being available after startup of the device) does not require any special setup. All that needs to be done is selecting the correct device in the IDE, which is "Cyclone V", and start the debug session.
Connecting to core 1
Before J-Link can connect to core 1, please make sure that the application running on core 0 has already released core 1 from reset. Otherwise, debugging will not be possible. By default, J-Link will connect to core 0 when selecting "Cyclone V" as device. In order to connect to core 1, just specify the J-Link script file from below to be used for the debug session that shall debug core 1. For more information about how to use J-Link script files in various environments, please refer to UM08001 (J-Link User Guide), chapter Executing J-Link script files.
RTT is supported on the Cortex-A9 of the Intel Cyclone V (Cortex-A9) target device. For more information about RTT on Cortex-A/R based devices, see Using RTT on Cortex-A/R based devices (AN08005)
For RTT on the Cyclone V, AP (AHB-AP) needs to be used.