General information about tracing
ARM tracing describes an advanced debug feature set of ARM devices that are able to stream out compressed core instruction information so a data stream of executed instructions can be reconstructed. This enables the possibility to analyze passed core instructions precisely and depending on the trace type without any gaps. In some ways this debug technique is comparable to an "application time machine" as all instructions from application start till stop are part of that trace stream and can be analyzed.
A full trace stream can only be reconstructed if the programmed application is known by the debug probe as the trace stream will mostly consist of information about what memory area is being executed from and how many instructions have been executed and how many weren't. To be able to synchronize the trace stream indicators such as the program counter will be transferred periodically as well.
The different trace types
Generally tracing is divided into the following three main trace types:
SWO (Serial Wire Output) is mostly used for printf debugging. But it offers more than that. For example periodic PC trace information can be output as well. That way a trace stream can be reconstructed from one "PC ping" to another using the ITM (Instrumentation Trace Macrocell). Unfortunately this leads to a incomplete trace stream due to the sampling frequency being relatively low. Other drawbacks are that SWO needs a physical hardware pin and is susceptible for overflows if the PC sampling frequency is set to fast. The biggest advanted is that the SWO protocol is widely supported by different debug probes and debug software.
The MTB (Micro Trace Buffer) was first introduced with Cortex-M0+ cores and enabled complete instruction trace for Cortex-M cores. This has been expanded with the newer ETB (Embedded Trace Buffer) and the latest ETF (Embedded Trace FIFO) which is part of the TMC (Trace Memory Controller).
All three versions are essentially designated memory areas in RAM (sometimes dedicated, sometimes shared) where the instruction trace data gets dumped into from the ETM (Embedded Trace Macrocell). That way you will get a complete trace stream of the last couple of instructions that will fit into that RAM area (usually only 4-8 kB in size). The memory gets overwritten in FIFO fashion which enables you to have the latest instructions stored.
A big plus of this technique is that you don't need any hardware pins at all and that you get a full trace coverage of the latest instruction trace that fit into RAM. The drawback is that you only get the latest instruction trace that fit into RAM which limits the actual time which can be analyzed backwards.
ETM and PTM (Program Trace Macrocell) are the key components that are generating the instruction trace data. ETM is most prominently available on Cortex-M and Cortex-R cores and PTM on Cortex-A cores (there are some exceptions also available on the market).
Instead of dumping the instructions into a RAM buffer an ETM/PTM can also send the information to the trace debug probe using GPIO pins directly. This technique is usually also referred to as pin trace. That way high speed transfers of more than 100 MByte/s can be achieved. The trace clock is generally half the CPU clock of the target device and gets sampled in DDR (double data rate) fashion.
This way you are not only getting the full trace stream but also with very high speeds so even high end Cortex-A devices with over 1 GHz CPU clock speed can be traced and analyzed during run time. The only drawback with this technique is that several high speed GPIO pins need to be available which are blocked by this technique during debugging (usually five pins, minimum two).
More information about tracing can be found in the J-Link User Manual (UM08001_JLink) or on our Website www.segger.com.