J-Link CoreSight

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CoreSight is a standard from ARM to describe debug components in a system and make them auto-detectable for the debug probe / debugger. CoreSight was introduced with the Cortex-M cores from ARM and new cores have been released as CoreSight compatible ones ever since. A basic feature of the CoreSight spec. is that components are all memory-mapped and therefore easily addressable by the debugger. It further specifies so-called ROM tables which can be scanned by a debugger to automatically find out what components are present in a connected system.

CoreSight SoC-600

While versions before CoreSight SoC-600 (SoC-200, SoC-400, ...) have been mainly backwards compatible and did not really require changes on the side of the debug probe, with CoreSight SoC-600 there is no backward compatibility as some low-level operations have been changed significantly.

J-Link support

J-Link supports CoreSight since the first Cortex-M cores have been released.

All current (2021) hardware revisions of J-Link / J-Trace also support CoreSight SoC-600 based systems. Be them ARM only setups or hybrid setups like ARM Cortex-M + RISC-V being in there.