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This article handles J-Link related RISC-V specifics. It is assumed that RISC-V as a term is already known. For more generic information about RISC-V, please refer to the RISC-V knowledge base article

Watchpoint support

J-Link supports data breakpoints (watchpoints) for RISC-V CPUs which are based on the V0.13 standard of the RISC-V debug spec. In general, the following combinations are possible for a watchpoint:

  • Addr == EXACT, Data == EXACT
  • Addr == EXACT, Data == ANY
  • Addr == EXACT, Data == RANGE
  • Addr == RANGE, Data == EXACT
  • Addr == RANGE, Data == ANY
  • Addr == RANGE, Data == RANGE
  • Addr == ANY, Data == EXACT
  • Addr == ANY, Data == ANY
  • Addr == ANY, Data == RANGE

Note: Right now, only the ones shown in bold are supported by J-Link

RISC-V behind a CoreSight DAP

The official debug spec. for RISC-V only describes how to implement a RISC-V debug interface via JTAG and a DM. The topology looks like this:

JTAG TAP -> DM -> DMI registers

However, for hybrid designs where there are for example ARM cores next to the RISC-V in the same system, it makes sense to put the RISC-V behind a DAP; so the ARM cores and the RISC-V can be accessed via the same debug connector and also other protocols like SWD can be supported this way. The topology looks like this:

JTAG/SWD -> SWJ-DP -> APB-AP -> DMI registers


When using RISC-V behind a DAP, some considerations need to be taken into account.

DMI registers base address

In contrast to an ARM core, for the RISC-V there are no ROM tables etc. from which J-Link could determine the base address of the DMI registers. By default, J-Link will assume 0x00000000 as the base address for the DMI registers if a RISC-V behind a DAP is found. You may specify a different base address via J-Link script files. Such a script file would look like this:

int InitTarget(void) {
  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x0");   // Base address where DMI registers can be found in the APB address space
  JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 0");  // Use AP[x] to communicate with the RISC-V
  return 0;

For more information about J-Link script files and how to use them, please refer to the wiki article: J-Link script files

JTAG chains

When using cJTAG / JTAG as target interface, J-Link by default tries to identify the CPU-TAP by its TAPId to know which TAP to communicate with to control the RISC-V core. While for most cores like ARM, the TAPId is more or less standardized, for RISC-V almost every vendor does their own TAPId.

If for example the JTAG chain consists of a single TAP with IRLen == 5, J-Link assumes that this TAP is the CPU-TAP. However, in case there is a JTAG chain with multiple TAPs that have IRLen == 5 but none of the TAPIds is known to J-Link, the TAP to connect to needs to be manually specified by the user.

The easiest way to manually specify the JTAG chain and TAP to connect to is a J-Link script file. Below are two example script for a JTAG chain that consists of 2 CPU-TAPs (each a RISC-V with IRLen == 5) that specifies to connect to TAP #0 or #1 resprectively.