The ARM CoreLink SSE-200 is a prototyping platform from ARM that allows prototyping of Cortex-M33 based devices on the ARM MPS3 board. It incorporates a dual-core Cortex-M33, lots of internal RAM (> 2 MB) and QSPI flash.
J-Link supports the MediatTek 7697 series since the following J-Link software versions:
- V6.35a and later (Download latest version)
Unfortunately, on the MediaTek 7697 series the standard Cortex-M software triggered reset via AIRCR.SYSRESETREQ does not work (bit has no effect).
A reset via the reset pin cannot be used because it also resets the debug logic (e.g. vector catch etc. bits) which makes it impossible to halt the core immediately after reset, before it executes any instruction.
For this device series, J-Link will issue a reset of the Cortex-M4 core only (AIRCR.VECTRESET). No peripherals etc. are reset by this reset. The Cortex-M4 core is halted after the secondary bootloader has run and jumped to the firmware image at 0x10079000 in QSPI flash. It is halted before any instruction of the firmware image is executed.