NXP LPC86x
The NXP LPC86x are Arm Cortex-M0 single core devices.
Contents
Flash Banks
Internal Flash
| Device | Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|---|
| LPC864M201 | Internal flash | 0x0000_0000 | 64 KB | 
|
| LPC865M201 | Internal flash | 0x0000_0000 | 32 KB |
|
Code Read Protection
The NXP LPC86x devices come with a Code Read Protection (CRP).
- The CRP selection bits lie within the first sector of the flash (0x0000_02FC).
- Per default (erased value) CRP is not set.
The J-Link software offers two different loaders for the device:
| Loader name | Meaning |
|---|---|
| Default | The value programmed to the CRP address will be checked. If it is != 0xFFFF_FFFF, the programming attempt will be rejected with an error. |
| Allow security | The value programmed to the CRP address will not be checked. |
Careful consideration is advised when changing the CRP value.
- Any value besides 0xFFFF_FFFF (NO_CRP/CRP0) or 0x536A_AC95 (NO_ISP) will prevent a debug connection via debug pins, thus preventing J-Link to connect.
- CRP levels CRP1 and CRP2 will only be recoverable via ISP command (USART).
- CRP level CRP3 will permanently lock the device. This mode is not recoverable (neither via SWD nor ISP)
Vector table verification
The NXP LPC86x devices come with a bootloader which will setup some device functionality and verify the image before jumping to the application. The image is verified via a CRC check of the first 6 vectors of the vector table (0x0000_0000 - 0x0000_001B). The 7th entry of the vector table (0x0000_001C) is expected to be the 2s complement of the first 6 entries. If this is not the case, the bootloader will refuse to boot the image.
Vector Table Remap
The LPC86x devices allow vector table remapping of some sort. remapping is handled via the SYSCON, SYSMEMREMAP (0x4004_8000) registers MAP bits ([1:0]):
| MAP value | Description |
|---|---|
| 0x0 (reset value) | Bootloader Mode. Interrupt vectors are re-mapped to Boot ROM. |
| 0x1 | User RAM Mode. Interrupt vectors are re-mapped to Static RAM. |
| 0x2 (def value after BTL execution) | User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. |
Watchdog Handling
- The device has a watchdog (WWDT).
- If the watchdog is enabled, it is fed during flash programming.
Device Specific Handling
Reset
The device uses custom reset:
- A watchpoint (WP) is set on the SYSCON.SYSMEMREMAP register
- The device is reset via AIRCR.SYSRESETREQ
- When the WP is hit, the application vector table has been mapped to 0x0
- The validity of the application vector table is checked (see Vector Table Remap)
- Image is valid:
- A breakpoint (BP) is set on the reset vector address read from 0x0000_0004.
- The target is started and J-Link waits until the target is halted on the reset vector.
- Image is invalid:
- Execution stops => Target is kept halted after the reset vector table remap operation.
