NXP i.MX 8M Nano

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The NXP i.MX 8M Nano are embedded multi-core processors consisting of one Cortex-M7 and up to four Cortex-A53.

External Boot Devices

Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8M Nano family comes with a variety of multi-core options listed in the following table:

Core J-Link Support
4 x Cortex-A53 YES.png
1 x Cortex-M7 YES.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-A53 core(s)

Init/Setup

The core(s) are enabled after boot.

Reset

Core reset is not performed.

Attach

Attach is supported.

Cortex-M7 core(s)

Init/Setup

The core(s) are enabled after boot. During connect the M7 is set to execute an endless loop at 0x00000000 (TCM RAM).

Reset

Reset is performed by using device-specific registers, than target CPU is halted.

Attach

Attach is not supported by default because the J-Link initializes certain RAM regions.

Device Specific Handling

Connect

After the boot stage J-Link writes an "infinite loop" code to the start of the M7s TCM RAM.

Evaluation Boards

Example Application