NXP i.MX 93
The NXP iMX 93 are applications processors integrating up to 2 Arm Cortex-A55 cores, ARM Cortex-M33 core and ARM Ethos-U65 microNPU neural-network core for cost-effective and energy-efficient ML applications.
Contents
ECC RAM
- ECC TCM and ECC Cache features of Cortex-M33 are enabled during connecting to the target device.
Configurable TCM size
- User application should ensure configured TCM size before using it.
Multi-Core Support
- Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX 93 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| 2x Cortex A-55 | 
|
| 1x Cortex M-33 |
|
| 1x Ethos-U65 | 
|
The iMX 93 devices have selectable core to boot the system: Cortex-A55 or Cortex-M33.
- If Cortex-A55 is selected as boot core, both A55 and M33 are powered.
- If Cortex-M33 is selected as boot core, A55 core is powered down.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A55
Init/Setup
- The target device must contain a valid boot-image that performs initial configuration and enables debug access.
Reset
- Core reset is not performed.
Attach
- Attach to a running target is supported only assuming it is already configured by bootloader/OS kernel.
Cortex-M33
Init/Setup
- Cortex-M33 clock must be enabled by the bootloader/OS kernel before it can be used for debugging.
Reset
- Core reset is not performed.
Attach
- Attach is supported.
Device Specific Handling
Limitations
- Some U-Boot/Linux images can reconfigure SWD/JTAG pins restricting access to the debug components. Please refer to the corresponding silicon/board vendor in order to get information about SWD/JTAG configuration.
