NXP i.MX 95
The NXP iMX 95 are applications processors integrating up to 6 Arm Cortex-A55 cores, ARM Cortex-M7, ARM Cortex-M33, ARM Mali GPU, 4K VPU, ISP, ML acceleration NPU, and Edgelock secure enclave security.
Contents
ECC RAM
- ECC TCM and ECC Cache features of Cortex-M33 are enabled during connecting to the target device.
Configurable TCM size
- User application should ensure configured TCM size before using it.
Multi-Core Support
- Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX 95 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| 6x Cortex A-55 | 
|
| 1x Cortex M-33 |
|
| 1x Cortex M-7 |
|
| 1x Mali GPU | 
|
| 1x Neutron NPU |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A55
Init/Setup
- Cortex-A55 cores must be enabled by the bootloader before it can be used for debugging.
Reset
- Core reset is not performed.
Attach
- Attach to a running target is supported only assuming it is already configured by bootloader/OS kernel.
Cortex-M7
Init/Setup
- Cortex-M7 clock must be enabled by the bootloader/OS kernel before it can be used for debugging.
Reset
- Core reset is not performed.
Attach
- Attach is supported.
Cortex-M33
Init/Setup
- The target device must contain a valid boot-image that performs initial configuration and enables debug access.
Reset
- Core reset is not performed.
Attach
- Attach is supported.
Device Specific Handling
Limitations
- Some U-Boot/Linux images can reconfigure SWD/JTAG pins restricting access to the debug components. Please refer to the corresponding silicon/board vendor in order to get information about SWD/JTAG configuration.
