This page refers to the Reneas RZ/G1E (Cortex-A7 dual core) and RZ/G1M (Cortex-A15 dual core) processors. It provides examples to connect to the different cores as well as a J-Flash project + custom RAMCode, which allows to program any common SPI flash conntected to the (Q)SPI controller of the MCU.
RZ/G1 QSPI flash programming
The (Q)SPI memory controller of the RZ/G1 device family does *not* allow to read the content of the connected SPI flash, memory mapped. For this reason, direct flash programming (e.g. from within an IDE or J-Link Commander) is not possible. However, programming can be done using J-Flash as it allows to remap the content of the connected SPI flash to a virtual memory map. SEGGER has created an example J-Flash project (including a custom RAMCode) for the RZ/G1 which allows programming of any common SPI flash connected to the (Q)SPI flash controller of the MCU. No further special handling is required. A list of all supported SPI flashes can be found here: https://www.segger.com/jlink_supported_devices.html#SupportedSPIFlashes
Below, the sample project including the custom RAMCode is available for download. It has been created and tested on the Y-RZG1-E-SEBA-A evaluation board. Following steps are required:
- Open project in J-Flash
- Open any data file to program in J-Flash
- Start programming using Auto (F7)
RZ/G1 Dual core debugging
The Renesas RZ/G1 is a dual core device. There are two variants of the RZ/G1:
- RZ/G1E dual core Cortex-A7
- RZ/G1M dual core Cortex-A15
By default, only one core (main core) is running which needs to release the second core from reset from within the application running on the main core.
Due to design limitations of the device, the second core cannot be easily enabled independently from the main core, via J-Link.
Dual core debugging on the RZ/G1
In order to debug both cores on the RZ/G1, the following needs to be done:
- Start a debug session for the main core, which uses the appropriate ConnectCore0 script
- Once the debug session has been started, it will have the second core enabled for debugging
- Start a debug session for the second core, which uses the appropriate ConnectCore1 script
- From now on, both cores can be debugged in parallel in both debugger instances
Script Files and sample projects
Below some sample script files for the dual core debugging as well as some sample projects for emIDE (V2.20 or later) and IAR EWARM (V7.40 or later) are available for download