The Renesas RZ/V2L is equipped with a Cortex-A55 (dual or single) CPU + a Cortex-M33 CPU.
- By default, the Cortex-M33 core is not enabled. In order to establish a connection, the J-Link performs a device specific connect sequence. After executing the sequence, the Cortex-M33 is executing a test loop in the SRAM. This way, the Cortex-M33 can be debugged out-of-the-box without the need of having a application running on the main core which enables the Cortex-M33.
- A device specific reset is performed which resets the M33 + performs the Cortex-M33 enable sequence. The Cortex-A55 is not affected by the reset.
The J-Link software supports the Cortex-M33 core, only.