SPI Flash

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The following article assumes that there is a basic understanding of what an SPI flash is. There are two major concepts of connecting an SPI flash to a MCU, where this article mainly refers to the latter one (Quad Mode):

Connection Methods

Pinout

All SPI flashes provide the following pins for communication:

Pin Description
CLK Serial Clock. Clock for the SPI flash.
MOSI Master-Out-Slave-In. Output of CPU and input of SPI flash.
Used to transmit data + command from CPU to SPI flash device. 1-bit is transmitted per clock.
MISO Master-In-Slave-Out. Output of SPI flash and input of CPU.
Used to transmit data SPI flash device to CPU.
nCS Chip-select (active low). Controlled by CPU, input for SPI flash.
While HIGH, all commands + data is ignored by SPI flash.

Many modern SPI flashes also provide the following (additional) pins:

Pin Description
DQ0 (MOSI) Used as I/O pin in address, dummy cycle and data phase of commands that support quad mode.
Used as MOSI during command phase and for commands that only work in serial mode.
DQ1 (MISO) Used as I/O pin in address, dummy cycle and data phase of commands that support quad mode.
Used as MISO during command phase and for commands that only work in serial mode.
DQ2 Used as I/O pin in address, dummy cycle and data phase of commands that support quad mode.
May have reset or other functionality for commands that do not use/support quad mode.
DQ3 Used as I/O pin in address, dummy cycle and data phase of commands that support quad mode.
May have reset or other functionality for commands that do not use/support quad mode.

Serial Mode - 4-pin Interface (Traditional)

The SPI flash is connected to an SPI unit of the CPU via CLK, MOSI, MISO, nCS pins. This is the minimum connection needed to store data on the SPI flash and get data from it. This connection actually works with any CPU that provides an SPI unit. The SPI flash can only be accessed by explicitly sending commands to it via the SPI unit, in order to erase/program or read the flash. The user software needs to manually copy SPI flash contents over to RAM and jump to them, in case code stored in the SPI flash, shall be executed.

Quad Mode (QSPI) - 6-pin Interface (Modern)

The SPI flash is connected to a dedicated QSPI unit of the CPU via CLK, DQ0, DQ1, DQ2, DQ3, nCS pins. The specific QSPI unit contains some logic that handles the communication with the SPI flash and makes it readable through the normal address space of the CPU. This way, the CPU can directly fetch instructions from the SPI flash, without manually need to care about reading out and copying over contents from the SPI flash. Usually, the QSPI unit is configured by the application or CPU at startup, to match the command set and requirements (dummy cycles etc.) of the connected SPI flash. From there on, it can be accessed like normal read-only memory (ROM) by the CPU. This combines the advantages of a parallel flash memory (accessible via address space of CPU) and a SPI flash (low pin count). As almost all SPI flashes nowadays can handle >= 100 MHz SPI clock frequencies (allowing an theoretically transfer speed of 400 MBit/s when using the SPI flash in quad mode where 4 data bits are transmitted per SPI clock) of and the dedicated QSPI controller usually provides some caching mechanisms to allow efficient instruction fetching and data loading from the SPI flash, the advantages of parallel flashes (even higher speed) is not that important anymore. Note that it depends on the actual MCU if a flash can be connected that way because a dedicated QSPI controller which makes the SPI flash memory-mapped visible, needs to be provided by the MCU.

J-Link Flash Download and Flash Breakpoints Support

For flashes connected via the 6-pin QSPI interface to a dedicated QSPI controller of the MCU that makes the SPI flash visible in the MCU's address space and therefore makes SPI flash executable, the J-Link features "Flash Download" as well as "Unlimited Number of Breakpoints in Flash" are supported. However, some limitations apply when using these features. For more information, please see here

Limitations When Using Flash Download and Flash Breakpoints

When using these J-Link features in SPI flash memory, some limitations need to be taken into account, which are explained in the following.

XIP Mode - Fast Read Mode

Many modern SPI flashes support a so-called XIP mode where XIP stand for execute-in-place. In this mode the SPI flash is in some kind of read-only mode.

Usually, an SPI flash operation consists of 4 phases:

  1. 1-byte command
  2. 3- or 4-byte address
  3. 1 or more dummy cycles (actual number of dummy cycles depends on command and on the used flash device)
  4. 1 or more data bytes

In XIP mode, the 1-byte command phase is omitted, to save some bandwidth. As there is no real standard regarding how to enter/exit XIP mode and this is different for various flashes, the flashloaders that are shipped with the J-Link software package do not support programming of SPI flash when it is in XIP mode. In order to support programming of a specific SPI flash that is in XIP mode, a specific flashloader for that specific SPI flash is needed. There are the following options to get such a flashloader:

  1. You write flashloader on your own and tell the J-Link software to use it. For more information, please refer to J-Link User Guide, chapter "Adding Support for new devices".
  2. Have SEGGER write a flashloader for you (NREs may apply). Please get in touch with info@segger.com

Note: XIP mode must not be confused with the capability of directly executing code from SPI flash. This functionality is also available if the flash is not in XIP mode as the QSPI controller of the MCU handles the SPI <-> memory mapped access translation. XIP mode of flash memory is just an optimization to reduce some SPI protocol overhead.

Quad Mode

As mentioned above, an SPI flash operation can be divided into different phases. By default, all phases are executed in serial mode, meaning data is transmitted to the SPI flash via MOSI (DQ0) and received by the CPU via MISO (DQ1), meaning one bit is transmitted per SPI clock. There are some read commands that allow to transmit the address + dummy cycle + data phase in quad mode (4-bits per SPI clock), meaning data throughput is 4 times the one in serial mode. However, some flashes also support a "quad protocol" where all phases for all commands are transmitted in quad mode. All SPI flashes by default boot in serial mode to allow to use a generic protocol to communicate with these flashes. For some of SPI flashes it is possible to configure them via non-volatile configuration bits to boot using the quad protocol, by default, making things slightly faster because some clocks are saved during command transmission, but also making things non-generic and flash device specific because not all flashes support this mode, there is no standard how to enter this mode, there is no possibility for the QSPI controller of the MCU to detect if this mode is active (it needs to be known) The flashloaders that are shipped with the J-Link software package do not support the quad protocol for all commands. In general, the small performance improvement by using quad protocol for the command phase as well, is not that significant that it is worth losing J-Link flash download support and general portability, in return.

Note: Quad I/O read commands that use all 4 pins for address, dummy cycle and data phase are supported though, as these are separate commands that do not affect the behavior of standard commands, supported by all flashes.

In order to support programming of an SPI flash with quad protocol for all commands, a specific flashloader for that specific SPI flash is needed. There are the following options to get such a flashloader:

  1. You write flashloader on your own and tell the J-Link software to use it. For more information, please refer to J-Link User Guide, chapter "Adding Support for new devices".
  2. Have SEGGER write a flashloader for you (NREs may apply). Please get in touch with info@segger.com