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This article describes device specifics of the ST STM32L5 series devices. The STM32L5 devices are Cortex-M33 based low power MCUs.


The following flash regions are supported by J-Link.

Device State Range Total size
Main flash memory
STM32L5xxxC Secure 0x0C00_0000 - 0x0C03_FFFF 256 KB
Non-secure 0x0800_0000 - 0x0803_FFFF
STM32L5xxxE Secure 0x0C00_0000 - 0x0C07_FFFF 512 KB
Non-secure 0x0800_0000 - 0x0807_FFFF
QSPI programming[1]
All --- 0x9000_0000 - 0x903F_FFFF (max) 4 MB (max)

Dualbank Flash Programming

The ST STM32L5 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte DUALBANK. By default, the value of this option byte is DUALBANK == 1, which means that the flash is configured as dual bank memory while DUALBANK == 0 means that the flash is configured as single bank memory flash. In dual-bank mode, the flash boot source can be switched between bank 1 or bank 2. In single-bank mode, flash always boots from bank 1. The total flash size is exactly the same for both modes. Another advantage of using DUALBANK is that both banks can be accessed in parallel (e.g. reading bank 1 while programming bank 2).

Problem description

The flash algorithm has to behave differently, depending on the active flash bank mode configuration as the flash controller expects different page indices for the same destination address.


When using the J-Link flash loader, make sure that the flash controller is configured for dual bank flash layout (DUALBANK == 1), which is the default.

(Octa)SPI support

The ST STM32L5xxx device series comes with a OCTASPI controller which allows memory mapped read accesses to any (Octa)SPI flash, connected to the Octa-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Octa-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the pins used to connect the SPI flash are not defined. Different pins can be used for the same (Octa)SPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm based on the ST STM32L562E-DK evaluation board. This flash algorithm can be used to to program any common (Octa/QSPI)SPI flash, connected to the Octa-SPI interface of the ST STM32L5xx device. The flash algorithm is implemented within our JLinkARM.dll In case a pin configuration, different from the one used in the example flash algorithm, is required, please get in touch with SEGGER directly via our support system:
For further information regarding this as well as the flash algorithm, please refer to the following pages:


Flash programming with TrustZone enabled (TZEN = 1) is supported.
RDP level 0 and 0.5 is also supported. The RAMCode is only usable with RDP level 0, for RDP level 0.5 a RAMless flashloader has to be used. This is a technical limitation. The J-Link software is not able to decide at runtime when to use the RAMCode or RAMless flashloader. If you want to use the RAMless flashloader for RDP 0.5, you have to add "_RAMLess" to the device name, e.g. use "STM32L552ZE_RAMLess" instead of "STM32L552ZE". Please note that a significantly lower programming speed has to be expected with the RAMless flashloader.


For the STM32L5 devices, the Cortex-M default reset strategy is used.

Debug specific

Please refer to the generic STM32 article.

Option byte programming

Direct option byte programming is not (yet) implemented for the ST STM32L5. However, the same method used to lock/unlock the devices can be used as described in Securing/unsecuring the device can be used to adjust any option bytes.

Securing/unsecuring the device

Please refer to the generic STM32 article.