SiFive Arty FPGA Dev Kit

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This article describes specifics for the SiFive Arty FPGA Dev Kit.

Preparing for J-Link

The SiFive Arty FPGA Dev Kit does not come with a standard debug connector but populates the debug JTAG signals on a custom connector. Therefore, it needs to be manually wired in case J-Link shall be connected to it.

In the following, it is described how the pins of connector JD on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link.

Wiring connection
Pin ARTY Pin J-Link Description
1 13 TDO
2 3 nTRST
3 9 TCK
7 5 TDI
8 7 TMS
9 15 nRESET
11 4 GND
12 1 VTref

Note: The pins on the JD connector are numbered as follows:

6 5 4 3 2 1
12 11 10 9 8 7

Wiki-sifive arty board.png

Debugging in FreedomStudio

TBD

Example project for FreedomStudio

TBD