Silicon Labs EFR32xG23

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The EFR32xG23 device family from Silicon Labs are Cortex-M33 based microcontrollers.

On-Chip Memory Regions

The EFR32xG23 series devices have an internal flash of up to 512 KiB size and a user data page (UDP) of 1 KiB. J-Link supports flash programming for both the internal flash and UDP.

Device Family Device name Internal flash size (KiB) Internal flash memory region User data page size (KiB) User data page memory region
Flex Gecko EFR32FG23AxxxF256 256 0x08000000 - 0x0803FFFF 1 0x0FE00000 - 0x0FE003FF
Flex Gecko EFR32FG23AxxxF512 512 0x08000000 - 0x0807FFFF 1 0x0FE00000 - 0x0FE003FF
Flex Gecko EFR32FG23BxxxF128 128 0x08000000 - 0x0801FFFF 1 0x0FE00000 - 0x0FE003FF
Flex Gecko EFR32FG23BxxxF512 512 0x08000000 - 0x0807FFFF 1 0x0FE00000 - 0x0FE003FF
Zen Gecko EFR32ZG23AxxxF512 512 0x08000000 - 0x0807FFFF 1 0x0FE00000 - 0x0FE003FF
Zen Gecko EFR32ZG23BxxxF512 512 0x08000000 - 0x0807FFFF 1 0x0FE00000 - 0x0FE003FF

Evaluation Boards

Example Application

Tracing on EFR32ZG23xxx series

This section describes how to get started with trace on the SiLabs EFR32ZG23xxx MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).


  • The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
  • The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
  • In order to rebuild the sample project, SEGGER Embedded Studio can be used.
  • The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system:

Tracing on SiLabs EFR32ZG23xxx

Minimum requirements

In order to use trace on the ST EFR32ZG23xxx MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.88h or later
  • Ozone V3.30 or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project has been tested with the minimum requirements mentioned above and a SiLabs BRD4204C Rev 00 Board on a PCB4001 Rev 03 motherboard.

Example project:

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality
Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time