Tracing on Hilscher netX90
This article describes how to get started with trace on the Hilscher netX90 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Hilscher netX90 MCU implements tracing via pins , so a J-Trace can be used for tracing.
In order to use trace on the Hilscher netX90 MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.46f or later
- Ozone V2.62e or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later
- Tracepin connection like on the NXHX 90-JTAG eval board (See Specifics/Limitations for more information)
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a NXHX 90-JTAG board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Pin trace on this target device can only be used with SWD, not with JTAG as some JTAG pins are shared with trace pins on this target device.
On the eval board used for this example the trace pins share functionality with status LEDs. When designing your own trace board we recommend not to share the trace lanes with other functionality to reduce possible signal integrity issues of the high frequency trace signals.
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.