Tracing on Infineon Traveo II (CYT2B7)

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This article describes how to get started with trace on the Infineon Traveo II (CYT2B7) MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Infineon Traveo II (CYT2B7) MCU implements tracing via pins, so a J-Trace can be used for tracing.

Minimum requirements

In order to use trace on the Infineon Traveo II (CYT2B7) MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.60f or later
  • Ozone V3.26b or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V2.0 or later

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Sample projects

The following sample projects are designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The projects have been tested with the minimum requirements mentioned above and a CYTVII-B-E-1M-176-CPU eval board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.

The Infineon CYT2B7 is a dual core device with a Cortex-M4 and Cortex-M0+ which both have different trace capabilities.

Cortex-M4 Core

Streaming Trace:

Buffer Trace:

Cortex-M0+ Core

Buffer Trace:

Note: Some examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system:

You can also create your own JLink Script file. How is explained here: How_to_configure_JLinkScript_files_to_enable_tracing

Tested Hardware


Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time