Tracing on ST STM32F769

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This article describes how to get started with trace on the ST STM32F769 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The ST STM32F769 MCU implements tracing via pins , so a J-Trace can be used for tracing.

Minimum requirements

In order to use trace on the ST STM32F769 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V6.18c or later
  • Ozone V2.46a or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later
  • Tracepin connection like on the STM32F769I-Evalboard (See Specifics/Limitations for more information)

Sample project

Streaming trace

The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a ST STM32F769I-EVALBOARD. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.

The following example project is generic without any PLL init and can be used with any STM32F7 device: ST_STM32F769_TraceExample_noPLLInit.zip


The maximum supported trace clock speed on the tested evalboard is 50 MHz due to hardware limitations (see ST manual for more information). Theoretically full 108 MHz traceclock should be possible if the target hardware is setup accordingly.


Here an example with 50 MHz traceclock: ST_STM32F769_EVAL_50MHz_TraceExample.zip

Here is one with 108 MHz traceclock: ST_STM32F769_EVAL_108MHz_TraceExample.zip

To use the 108 MHz example make sure that no peripherals are connected to the trace lines. If you are using the ST STM32F769I-EVALBOARD check the manual for the needed modifications to enable higher trace speed.


Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source it can be requested at support@segger.com

Specifics/Limitations

The STM32F7xx Productfamily has additional pins that can be used for tracing. Usually only 5 Pins are mapped to have the trace functionality. In this case however multiple pinout configurations are possible over different ports even. Should you be using our trace example make sure your physical tracepin connections are equal to the ones on the ST STM32F769I-EVALBOARD. If not adjust the pin initialization accordingly.

Tested Hardware

ST STM32F769I-EVALBOARD

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time