Difference between revisions of "SemiDrive D32xx"
Arne.kulinna (talk | contribs) (Created page with "__TOC__ The SemiDrive D32xx are Cortex-R5 based MCUs. ==Internal Flash== D32xx devices consist of a SIP and have an internal QSPI flash. Therefore programming the internal...") |
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The SemiDrive D32xx are Cortex-R5 based MCUs. |
The SemiDrive D32xx are Cortex-R5 based MCUs. |
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Latest revision as of 15:13, 15 May 2024
Contents
The SemiDrive D32xx are Cortex-R5 based MCUs.
Internal Flash
D32xx devices consist of a SIP and have an internal QSPI flash.
Therefore programming the internal flash requires special handling. For more information about this, please see the QSPI Flash Programming Support article.
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x10000000 | Up to 4 MB | 
|
ECC RAM
D32xx devices have ECC RAM which can be disabled. However, a connect to D32xx devices will initialize 1MB at 0x400000.
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
