Difference between revisions of "Infineon PMG1"

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{| class="seggertable"
  
{| class="seggertable"
 
|-
  
|-
−
! Flash Bank || Base address !! Size || J-Link Support
 +
! Subfamily || Devices || Flash Bank || Base address !! Size || J-Link Support
 
|-
  
|-
−
| Internal Flash || 0x00000000 || Up to 256 KB || style="text-align:center;"| {{YES}}
+
| PMG1-B1 || CYPM1115/1116 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}}
  +
|-
  +
| PMG1-S0 || CYPM1011 || Internal Flash || 0x00000000 || 64 KB || style="text-align:center;"| {{YES}}
  +
|-
  +
| PMG1-S1 || CYPM1111 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}}
  +
|-
  +
| PMG1-S2 || CYPM1211 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}}
  +
|-
  +
| PMG1-S3 || CYPM1311 || Internal Flash || 0x00000000 || 256 KB || style="text-align:center;"| {{YES}}
 
|}
  
|}
   
 
==Watchdog Handling==
  
==Watchdog Handling==
−
*The device does not have a watchdog.
 +
*The device has a watchdog WDT.
  +
*The watchdog is not fed during flash programming.
−
*The device has a watchdog [WATCHDOGNAME].
 
−
*The watchdog is fed during flash programming.
  
−
*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
  
−  
   
 
==Device Specific Handling==
  
==Device Specific Handling==
 
===Connect===
  
===Connect===
  +
The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:<br>
  +
* Reset mode: <br> J-Link toggles the XRES line and then sends SWD commands.<br>Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.<br>
  +
* Power Cycle mode:<br> J-Link powers on the target and then starts sending the SWD commands.<br>Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br>Make sure to set VSupply (pin 19) correctly before connecting it to the target board.<br>This is the only mode supported by PMG1-S0 devices.<br>
  +
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br>
  +
 
===Reset===
  
===Reset===
−
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
 +
*The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point.
−
*The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
  
−
*The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
  
−
*The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]].
  
−
*The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]].
  
−
*The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]].
  
−
*The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]].
  
−
*The device uses custom reset:.....
  
   
 
==Limitations==
  
==Limitations==
−
===Dual Core Support===
  
−
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
  
 
===Attach===
  
===Attach===
−
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
 +
Attach is not supported because the J-Link resets the device on connect.
−
===Security===
  
   
 
==Evaluation Boards==
  
==Evaluation Boards==
  +
*[[Infineon_EVAL_PMG1_B1_DRP| EVAL_PMG1_B1_DRP]]
−
*[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]]
  
  +
*[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit | CY7110EZ-PD PMG1-S0 Prototyping kit]]
  +
*[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit | CY7110EZ-PD PMG1-S1 Prototyping kit]]
  +
*[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit | CY7110EZ-PD PMG1-S2 Prototyping kit]]
   
−
==Example Application==
  
−
*[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]]
  
   
−
== Tracing ==
 +
==Example Application==
  +
*[[Infineon_EVAL_PMG1_B1_DRP#Example_Project | EVAL_PMG1_B1_DRP]]
−
The following trace example projects are available:
  
  +
*[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S0 Prototyping kit]]
−
* [Link to Board Article1]
  
  +
*[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S1 Prototyping kit]]
−
* [Link to Board Article2]
  
  +
*[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S2 Prototyping kit]]
−
* ...
  

Latest revision as of 09:44, 14 May 2024

The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.

Flash Banks

Internal Flash

Subfamily Devices Flash Bank Base address Size J-Link Support
PMG1-B1 CYPM1115/1116 Internal Flash 0x00000000 128 KB YES.png
PMG1-S0 CYPM1011 Internal Flash 0x00000000 64 KB YES.png
PMG1-S1 CYPM1111 Internal Flash 0x00000000 128 KB YES.png
PMG1-S2 CYPM1211 Internal Flash 0x00000000 128 KB YES.png
PMG1-S3 CYPM1311 Internal Flash 0x00000000 256 KB YES.png

Watchdog Handling

  • The device has a watchdog WDT.
  • The watchdog is not fed during flash programming.

Device Specific Handling

Connect

The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:

  • Reset mode:
    J-Link toggles the XRES line and then sends SWD commands.
    Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.
  • Power Cycle mode:
    J-Link powers on the target and then starts sending the SWD commands.
    Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.
    Make sure to set VSupply (pin 19) correctly before connecting it to the target board.
    This is the only mode supported by PMG1-S0 devices.

A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.

Reset

  • The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point.

Limitations

Attach

Attach is not supported because the J-Link resets the device on connect.

Evaluation Boards


Example Application

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