Difference between revisions of "Infineon PMG1"
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| − | ! Subfamily || Flash Bank || Base address !! Size || J-Link Support |
+ | ! Subfamily || Devices || Flash Bank || Base address !! Size || J-Link Support |
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| − | | PMG1-B1 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
+ | | PMG1-B1 || CYPM1115/1116 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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| − | | PMG1-S0 || Internal Flash || 0x00000000 || 64 KB || style="text-align:center;"| {{YES}} |
+ | | PMG1-S0 || CYPM1011 || Internal Flash || 0x00000000 || 64 KB || style="text-align:center;"| {{YES}} |
| + | |- |
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| + | | PMG1-S1 || CYPM1111 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | PMG1-S2 || CYPM1211 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | PMG1-S3 || CYPM1311 || Internal Flash || 0x00000000 || 256 KB || style="text-align:center;"| {{YES}} |
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===Connect=== |
===Connect=== |
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The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:<br> |
The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:<br> |
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| + | * Reset mode: <br> J-Link toggles the XRES line and then sends SWD commands.<br>Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.<br> |
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| − | * Reset mode: <br> |
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| + | * Power Cycle mode:<br> J-Link powers on the target and then starts sending the SWD commands.<br>Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br>Make sure to set VSupply (pin 19) correctly before connecting it to the target board.<br>This is the only mode supported by PMG1-S0 devices.<br> |
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| − | J-Link toggles the XRES line and then sends SWD commands.<br> |
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| − | Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.<BR> |
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| − | |||
| − | * Power Cycle mode:<br> |
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| − | J-Link powers on the target and then starts sending the SWD commands. <br> |
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| − | Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br> |
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| − | Make sure to set VSupply (pin 19) correctly before connecting it to the target board. <br> |
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| − | This is the only mode supported by PMG1-S0 devices.<br> |
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| − | <br> |
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A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br> |
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br> |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[Infineon_EVAL_PMG1_B1_DRP| |
+ | *[[Infineon_EVAL_PMG1_B1_DRP| EVAL_PMG1_B1_DRP]] |
| + | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
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| + | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
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| + | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
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| + | |||
==Example Application== |
==Example Application== |
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| − | *[[Infineon_EVAL_PMG1_B1_DRP#Example_Project | |
+ | *[[Infineon_EVAL_PMG1_B1_DRP#Example_Project | EVAL_PMG1_B1_DRP]] |
| + | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
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| + | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
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| + | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
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Latest revision as of 09:44, 14 May 2024
The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.
Contents
Flash Banks
Internal Flash
| Subfamily | Devices | Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|---|---|
| PMG1-B1 | CYPM1115/1116 | Internal Flash | 0x00000000 | 128 KB | 
|
| PMG1-S0 | CYPM1011 | Internal Flash | 0x00000000 | 64 KB |
|
| PMG1-S1 | CYPM1111 | Internal Flash | 0x00000000 | 128 KB |
|
| PMG1-S2 | CYPM1211 | Internal Flash | 0x00000000 | 128 KB |
|
| PMG1-S3 | CYPM1311 | Internal Flash | 0x00000000 | 256 KB |
|
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog is not fed during flash programming.
Device Specific Handling
Connect
The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:
- Reset mode:
J-Link toggles the XRES line and then sends SWD commands.
Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin. - Power Cycle mode:
J-Link powers on the target and then starts sending the SWD commands.
Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.
Make sure to set VSupply (pin 19) correctly before connecting it to the target board.
This is the only mode supported by PMG1-S0 devices.
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.
Reset
- The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point.
Limitations
Attach
Attach is not supported because the J-Link resets the device on connect.
Evaluation Boards
- EVAL_PMG1_B1_DRP
- CY7110EZ-PD PMG1-S0 Prototyping kit
- CY7110EZ-PD PMG1-S1 Prototyping kit
- CY7110EZ-PD PMG1-S2 Prototyping kit
