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17 July 2024
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10:11 | Xilinx Zynq UltraScalePlus 4 changes history +365 [Artjom.Kister (4×)] | |||
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10:11 (cur | prev) −1 Artjom.Kister talk contribs (→Example Application) | ||||
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10:08 (cur | prev) +126 Artjom.Kister talk contribs (→Example Application) | ||||
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10:02 (cur | prev) +239 Artjom.Kister talk contribs (→Init/Setup) | ||||
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09:56 (cur | prev) +1 Artjom.Kister talk contribs (→Init/Setup) | ||||
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10:05 | (Upload log) [Artjom.Kister (3×)] | |||
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10:05 Artjom.Kister talk contribs uploaded File:AMD Xilinx EK-U1-ZCU106-G R5 1 TestProject ES V814.zip | ||||
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10:04 Artjom.Kister talk contribs uploaded File:AMD Xilinx EK-U1-ZCU106-G R5 0 TestProject ES V814.zip | ||||
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10:04 Artjom.Kister talk contribs uploaded File:AMD Xilinx EK-U1-ZCU106-G A53 0 TestProject ES V814.zip | ||||
| 09:28 | J-Link cannot connect to the CPU diffhist +138 Leon talk contribs (→Test Connection) | ||||