Difference between revisions of "Realtek Ameba D"
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− | The '''Realtek Ameba D''' are dual core ( |
+ | The '''Realtek Ameba D''' are dual core (KM0/KM4) microprocessors with WIFI and Bluetooth. |
==Flash Banks== |
==Flash Banks== |
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! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
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− | | RTL872xCS |
+ | | RTL872xCS |
+ | RTL872xDN |
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+ | RTL872xDM |
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+ | || 0x08000000 || 16 MB || |
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*'''Default''' SCK@B13 CS@B16 D0@B14 D1@B17 |
*'''Default''' SCK@B13 CS@B16 D0@B14 D1@B17 |
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− | ==ECC RAM [OPTIONAL]== |
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− | *Describe ECC RAM restriction here. |
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− | == |
+ | ==Multi-Core Support [OPTIONAL]== |
+ | Flash programming is done by KM0 core (Cortex-M23).<br> |
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− | *Describe Vector Table Remap here.. |
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− | ==Watchdog Handling== |
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− | *The device does not have a watchdog. |
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− | *The device has a watchdog [WATCHDOGNAME]. |
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− | *The watchdog is fed during flash programming. |
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− | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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− | |||
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− | ==Multi-Core Support [OPTIONAL]== |
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− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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The [DeviceFamily]family comes with a variety of multi-core options.<br> |
The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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===Reset=== |
===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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+ | |||
− | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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− | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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− | *The device uses custom reset:..... |
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==Limitations== |
==Limitations== |
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Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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− | ===Attach=== |
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− | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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==Evaluation Boards== |
==Evaluation Boards== |
Revision as of 12:33, 6 March 2023
Contents
The Realtek Ameba D are dual core (KM0/KM4) microprocessors with WIFI and Bluetooth.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support | Limitations |
---|---|---|---|---|
QSPI | 0x08000000 | 4 MB | only for RTL872xDF devices |
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
RTL872xCS
RTL872xDN RTL872xDM |
0x08000000 | 16 MB |
|
Multi-Core Support [OPTIONAL]
Flash programming is done by KM0 core (Cortex-M23).
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project