Difference between revisions of "GigaDevice GD32A5"
Line 12: | Line 12: | ||
|- |
|- |
||
| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
||
+ | |- |
||
+ | | Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
||
|} |
|} |
||
+ | |||
==ECC RAM== |
==ECC RAM== |
||
− | |||
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
||
starting at 0x2000 0000. |
starting at 0x2000 0000. |
||
+ | ==Watchdog Handling== |
||
− | ==Supported Flash Banks== |
||
+ | *The device does have 2 watchdogs. |
||
− | ===Internal Flash=== |
||
+ | *The watchdogs are fed during flash programming. |
||
− | {| class="seggertable" |
||
− | |- |
||
− | ! Device || StartAddr || Size || J-Link Support |
||
− | |- |
||
− | | GD32A503xB || 0x08000000 || 128Kb || scope="col" style="text-align:center" | {{YES}} |
||
− | |- |
||
− | | GD32A503xC || 0x08000000 || 256Kb || scope="col" style="text-align:center" | {{YES}} |
||
− | |- |
||
− | | GD32A503xD || 0x08000000 || 384Kb || scope="col" style="text-align:center" | {{YES}} |
||
− | |} |
||
− | |||
− | ===Option Byte === |
||
− | {| class="seggertable" |
||
− | |- |
||
− | ! Device || StartAddr || Size || J-Link Support |
||
− | |- |
||
− | | GD32A503xx || 0x1FFFF800 || 24 Byte || scope="col" style="text-align:center" | {{YES}} |
||
− | |} |
||
+ | ==Device Specific Handling== |
||
− | ==Reset== |
||
+ | ===Connect=== |
||
− | The device uses normal reset, no special handling necessary. |
||
+ | ===Reset=== |
||
− | ==Minimum requirements== |
||
+ | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
||
− | * J-Link software V7.82b or later |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
− | *GigaDevice GD32A503-EVAL |
+ | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] |
==Example Application== |
==Example Application== |
||
+ | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] |
||
− | *GigaDevice GD32A503-EVAL evaluation board: https://wiki.segger.com/GigaDevice_GD32A503-EVAL#Example_Project |
Revision as of 11:56, 15 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Main flash Bank 0 | 0x08000000 | Up to 256 KB | |
Main flash Bank 1 | 0x08040000 | 128 KB | |
Option Byte 0 | 0x1FFFF800 | 24 B |
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.