Difference between revisions of "GigaDevice GD32A5"
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+ | The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® |
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+ | Cortex®-M33 processor. |
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__TOC__ |
__TOC__ |
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+ | |||
− | The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® |
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+ | ==Flash Banks== |
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− | Cortex®-M33 processor.<br> |
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− | ==Internal |
+ | ===Internal Flash=== |
{| class="seggertable" |
{| class="seggertable" |
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|- |
|- |
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− | ! |
+ | ! Flash Bank || Base address !! Size || J-Link Support |
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|- |
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+ | | Main flash Bank 0 || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}} |
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− | | GD32A503xB || 0x20000000 || 24Kb |
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+ | | Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
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− | | GD32A503xC || 0x20000000 || 32Kb |
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|- |
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+ | | Data flash || 0x08800000 || up to 64 KB || style="text-align:center;"| {{NO}} |
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− | | GD32A503xD || 0x20000000 || 48Kb |
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− | |} |
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− | |||
− | *** Additional information *** |
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− | In order to prevent errors when reading first time, the DLL intialises the first 24Kb of RAM |
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− | starting at 0x2000 0000. |
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− | |||
− | ==Supported Flash Banks== |
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− | ===Internal Flash=== |
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− | {| class="seggertable" |
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|- |
|- |
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+ | | Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
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− | ! Device || StartAddr !! Size || J-Link Support |
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+ | | Option Byte 1 || 0x4002 2068|| 4 B || style="text-align:center;"| {{NO}} |
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− | | GD32A503xB || 0x08000000 || 128Kb || YES |
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+ | | OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} |
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− | | GD32A503xC || 0x08000000 || 256Kb || YES |
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− | |- |
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− | | GD32A503xD || 0x08000000 || 384Kb || YES |
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|} |
|} |
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+ | ==ECC RAM== |
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+ | In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
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+ | starting at 0x2000 0000. |
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− | == |
+ | ==Watchdog Handling== |
+ | *The device does have 2 watchdogs. |
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− | {| class="seggertable" |
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+ | *The watchdogs are fed during flash programming. |
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− | |- |
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+ | |||
− | ! Device || StartAddr !! Size || J-Link Support |
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+ | ==Device Specific Handling== |
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− | |- |
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+ | ===Connect=== |
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− | | GD32A503xB || 0x1FFFF800 || 24 Byte || YES |
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+ | * On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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− | |- |
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− | | GD32A503xC || 0x1FFFF800 || 24 Byte|| YES |
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− | |- |
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− | | GD32A503xD || 0x1FFFF800 || 24 Byte|| YES |
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− | |} |
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− | ==Reset== |
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− | The device uses normal reset, no special handling necessary. |
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+ | ===Reset=== |
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+ | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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− | *GigaDevice GD32A503-EVAL |
+ | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] |
==Example Application== |
==Example Application== |
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+ | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] |
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− | *GigaDevice GD32A503-EVAL evaluation board: https://wiki.segger.com/GigaDevice_GD32A503-EVAL#Example_Project |
Revision as of 16:27, 16 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Main flash Bank 0 | 0x08000000 | Up to 256 KB | |
Main flash Bank 1 | 0x08040000 | 128 KB | |
Data flash | 0x08800000 | up to 64 KB | |
Option Byte 0 | 0x1FFFF800 | 24 B | |
Option Byte 1 | 0x4002 2068 | 4 B | |
OTP Bytes | 0x1FFF7000 | 1 KB |
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.