Difference between revisions of "Renesas RZ/A3UL"
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The Renesas RZ/A3UL family features a 64-bit Cortex-A55 core with a maximum operating frequency of 1 GHz |
The Renesas RZ/A3UL family features a 64-bit Cortex-A55 core with a maximum operating frequency of 1 GHz |
Latest revision as of 13:29, 15 May 2024
The Renesas RZ/A3UL family features a 64-bit Cortex-A55 core with a maximum operating frequency of 1 GHz
Flash
The RZ/A3UL does not come with an internal flash. Instead, the evaluation board features an external flash connected to the SPI Multi I/O interface:
- SPI Multi I/O (0x20000000; up to 128 MB)
The evaluation board offers two different flashes connected to the SPI Multi I/O interface:
- QuadSPI (16 MB)
- OctaSPI (128 MB)
For the RZ/A3UL, the J-Link Multiple Flashloader feature is used which allows to select from a pool of different loaders for the same flash bank. By default (no loader specified), the J-Link software uses the QuadSPI loader. Valid loader names are:
- R9A07G063U02GBG?BankAddr=0x20000000&Loader=QuadSPI --> (QSPI)
- R9A07G063U02GBG?BankAddr=0x20000000&Loader=OctaSPI --> (OSPI)
Reset
No special reset but the generic reset strategy is performed: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
Evaluation Boards
- Renesas RZ/A3UL SMARC EVK: https://wiki.segger.com/Renesas_RZ/A3UL_SMARC_EVK
Example Application
- TBD