Difference between revisions of "NXP MCX A"
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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− | | Internal Flash || 0x00000000 || up to |
+ | | Internal Flash || 0x00000000 || up to 1024 KB || style="text-align:center;"| {{YES}} |
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Revision as of 12:36, 27 May 2024
The NXP MCX A are single core ARM Cortex-M33 microprocessors.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00000000 | up to 1024 KB |
ECC Flash
- Device has ECC Flash, but no special handling required.
Watchdog Handling
- The device has 2 watchdogs WWDT and CDOG.
- The watchdog WWDT is fed during flash programming.
- No handling for CDOG implemented.
Device Specific Handling
Reset
- The J-Link performs a device specific reset sequence. SRAM and Flash is set to RWX.
Attach
Attach is supported.
Evaluation Boards
NXP MCX-A14X-EVK evaluation board