Difference between revisions of "Infineon EVAL PMG1 B1 DRP"
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__TOC__ |
__TOC__ |
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− | This article describes specifics for the |
+ | This article describes specifics for the Infineon EVAL PMG1 B1 DRP evaluation board.<br> |
+ | [[File:Infineon_EVAL_PMG1_B1_DRP_CYPM1116_board.jpg|450px]] |
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− | '''[PICTURE OF BOARD]''' |
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− | [[File:VENDOR_BOARDNAME.jpg|450px]] |
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== Preparing for J-Link == |
== Preparing for J-Link == |
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+ | |||
− | *Connect the J-Link to ...... |
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*Connect the J-Link to this pins: |
*Connect the J-Link to this pins: |
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{| class="seggertable" |
{| class="seggertable" |
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! J-Link Pin || Connector !! Pin || Name |
! J-Link Pin || Connector !! Pin || Name |
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|- |
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− | | VTref || || || |
+ | | VTref || J4 || 1 || B1_VDDD |
|- |
|- |
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− | | GND || || || |
+ | | GND || J4 || 2 || GND |
|- |
|- |
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− | | |
+ | | TMS/SWDIO || J4 || 9 || SWDIO |
|- |
|- |
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− | | |
+ | | TCK/SWCLK || J4 || 7 || SWDCLK |
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|- |
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− | | |
+ | | RESET || J4 || 5 || RESET |
− | |- |
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− | | TCK/SWCLK || || || |
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− | |- |
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− | | RTCK || || || |
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− | |- |
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− | | TDO/SWO || || || |
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− | |- |
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− | | RESET || || || |
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− | |- |
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− | | DBGRQ || || || |
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− | |- |
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− | | 5V-Supply || || || |
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− | |||
|} |
|} |
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− | *Power the board via... |
+ | *Power the board via J1 9...22V. |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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+ | [[File:Infineon_EVAL_PMG1_B1_DRP_CYPM1116-48LQXI_connect.png|400px]] |
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− | '''[PICTURE OF CONNECT]''' |
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− | [[File:VENDOR_DEVICE_CONNECT.PNG|400px]] |
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== Example Project== |
== Example Project== |
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====SETUP==== |
====SETUP==== |
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*Embedded Studio: V7.20 |
*Embedded Studio: V7.20 |
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− | *Hardware: |
+ | *Hardware: Infineon EVAL PMG1 B1 DRP |
− | *Link: [[File: |
+ | *Link: [[File:Infineon_CYPM1116_TestProject_ES_V720.zip]] |
− | |||
− | == Tracing on [DeviceName]== |
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− | This section describes how to get started with trace on the [SiliconVendor] [DeviceFamily] MCUs. |
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− | This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
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− | If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
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− | {{Note|1= |
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− | * The sample projects come with a pre-configured project file for Ozone that runs out-of-the box. |
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− | * The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace. |
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− | * In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
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− | * The examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
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− | ** To create your own .JLinkScriptfile you can use the following guide as reference: [[How_to_configure_JLinkScript_files_to_enable_tracing]] |
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− | }} |
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− | === Minimum requirements === |
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− | In order to use trace on the [SiliconVendor] [DeviceName] MCU devices, the following minimum requirements have to be met: |
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− | * J-Link software version Vx.xxx or later |
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− | * Ozone Vx.xxx or later (if streaming trace and / or the sample project from below shall be used) |
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− | * J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace |
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− | * J-Link Plus V12 or later for TMC/ETB trace |
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− | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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− | ==== Streaming trace ==== |
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− | The project below has been tested with the minimum requirements mentioned above and a ''[Boardname]''. |
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− | *'''Example project:''' [[Media:ExampleProject.zip | ExampleProject.zip]] |
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− | ==== Trace buffer (TMC/ETB) ==== |
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− | The project below is utilizing the on-chip trace buffer (it is '''not''' meant for streaming trace). |
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− | *'''Example Project:''' [[Media:ExampleProject.zip | ExampleProject.zip]] |
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− | ==== Tested Hardware ==== |
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− | [[File:Board.png|none|thumb|Board Name]] |
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− | ==== Specifics/Limitations(optional) ==== |
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− | The [BoardName] needs some modifications for all 4 trace data pins to work. For more information about this see the board specific user manual. |
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− | ==== Reference trace signal quality ==== |
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− | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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− | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
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− | If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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− | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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− | ===== Trace clock signal quality ===== |
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− | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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− | [[File:TCLK.png|none|thumb|Trace clock signal quality]] |
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− | ===== Rise time ===== |
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− | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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− | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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− | [[File:Risetime_TCLK.png|none|thumb|TCLK rise time]] |
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− | ===== Setup time ===== |
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− | The setup time shows the relative setup time between a trace data signal and trace clock. |
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− | The measurement markers are set at 50% of the expected voltage level respectively. |
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− | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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− | [[File:Setuptime_TD0.png|none|thumb|TD0 setup time]] |
Latest revision as of 10:37, 30 May 2024
This article describes specifics for the Infineon EVAL PMG1 B1 DRP evaluation board.
Preparing for J-Link
- Connect the J-Link to this pins:
J-Link Pin | Connector | Pin | Name |
---|---|---|---|
VTref | J4 | 1 | B1_VDDD |
GND | J4 | 2 | GND |
TMS/SWDIO | J4 | 9 | SWDIO |
TCK/SWCLK | J4 | 7 | SWDCLK |
RESET | J4 | 5 | RESET |
- Power the board via J1 9...22V.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the [SiliconVendor] [EvalBoardName].
It is a simple Hello World sample linked into the internal flash.
SETUP
- Embedded Studio: V7.20
- Hardware: Infineon EVAL PMG1 B1 DRP
- Link: File:Infineon CYPM1116 TestProject ES V720.zip