Difference between revisions of "Infineon CYT4BB"
(Created page with "'''CYT4BB (TVII-B-H-4M)''' is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU. == Flash memory layout == The CYT4BB series devices have 4...") |
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− | '''CYT4BB (TVII-B-H-4M)''' is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU. |
+ | '''CYT4BB (TVII-B-H-4M)''' is a subfamily of [[Cypress Traveo II device family | Traveo II]] microcontrollers containing a Cortex M7 and Cortex M0+ CPU. |
== Flash memory layout == |
== Flash memory layout == |
Revision as of 15:29, 31 March 2021
CYT4BB (TVII-B-H-4M) is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.
Flash memory layout
The CYT4BB series devices have 4160 KB Code flash and a 256 KB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
Flash | Start adress | End adress | Sector size | Sector count | Total size |
---|---|---|---|---|---|
Code flash large area | 0x10000000 | 0x103EFFFF | 32 KB | 126 | 4032 KB |
Code flash small area | 0x103F0000 | 0x1040FFFF | 8 KB | 16 | 128 KB |
Work flash large area | 0x14000000 | 0x1402FFFF | 2 KB | 96 | 192 KB |
Work flash small area | 0x14030000 | 0x1403FFFF | 128 B | 512 | 64 KB |