Difference between revisions of "Silicon Labs EFR32xG28"
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+ | [[Category:Device families]] |
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− | The '''Silicon Labs EFR32xG28''' are wireless SoCs based on Cortex-M33 microcontrollers. |
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+ | The '''Silicon Labs EFR32xG28''' are wireless SoCs based on Cortex-M33 microcontrollers. These MCUs are part of the [[Silicon Labs EFx32 Series 2 | EFx32 Series 2]] devices. |
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+ | |||
__TOC__ |
__TOC__ |
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+ | |||
+ | == EFx32 Series 2 specifics == |
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+ | Please refer to the [[Silicon Labs EFx32 Series 2]] article. |
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==Flash Banks== |
==Flash Banks== |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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− | | Internal flash || 0x08000000 || |
+ | | Internal flash || 0x08000000 || 1024 KB || style="text-align:center;"| {{YES}} |
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|- |
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| User Data || 0x0FE00000 ||1 KB || style="text-align:center;"| {{YES}} |
| User Data || 0x0FE00000 ||1 KB || style="text-align:center;"| {{YES}} |
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*The device has 2 Watchdogs, they are feed during programming, if they are enabled. |
*The device has 2 Watchdogs, they are feed during programming, if they are enabled. |
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− | ==Device Specific Handling== |
+ | == Device Specific Handling == |
− | |||
===Reset=== |
===Reset=== |
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+ | *The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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− | *The device uses custom reset with halt after bootloader. |
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− | === |
+ | === Security === |
+ | See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article. |
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− | * Attach is supported. |
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− | === |
+ | === Secure boot === |
+ | See: [[Silicon Labs EFx32 Series 2#Secure boot specific | Silicon Labs EFx32 Series 2]] article. |
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− | * If device is secured, User is offered an unsecure by mass erase. |
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==Evaluation Boards== |
==Evaluation Boards== |
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+ | * [[Silicon Labs BRD4271A]] |
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− | *Silicon Labs ERF32xG25 evaluation board: https://wiki.segger.com/Silicon_Labs_BRD4271A |
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==Example Application== |
==Example Application== |
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+ | * [[Silicon Labs BRD4271A#Example Project | Silicon Labs BRD4271A]] |
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− | *Silicon Labs evaluation board: https://wiki.segger.com/Silicon_Labs_BRD4271A#Example_Project |
Latest revision as of 13:23, 15 May 2024
The Silicon Labs EFR32xG28 are wireless SoCs based on Cortex-M33 microcontrollers. These MCUs are part of the EFx32 Series 2 devices.
Contents
EFx32 Series 2 specifics
Please refer to the Silicon Labs EFx32 Series 2 article.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal flash | 0x08000000 | 1024 KB | |
User Data | 0x0FE00000 | 1 KB |
Watchdog Handling
- The device has 2 Watchdogs, they are feed during programming, if they are enabled.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Security
See: Silicon Labs EFx32 Series 2 article.
Secure boot
See: Silicon Labs EFx32 Series 2 article.