Difference between revisions of "Infineon PMG1"
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− | ! Flash Bank || Base address !! Size || J-Link Support |
+ | ! Subfamily || Devices || Flash Bank || Base address !! Size || J-Link Support |
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− | | |
+ | | PMG1-B1 || CYPM1115/1116 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
− | |} |
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− | |||
− | ====ECC Flash [OPTIONAL]==== |
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− | *Describe ECC Flash restriction here. |
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− | |||
− | ===QSPI Flash=== |
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− | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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− | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. For details on how to select a specific flash loader, please see [[J-Link_Multiple_Flashloader#Selecting_a_specific_flashloader | here]]. |
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− | {| class="seggertable" |
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+ | | PMG1-S0 || CYPM1011 || Internal Flash || 0x00000000 || 64 KB || style="text-align:center;"| {{YES}} |
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− | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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+ | | PMG1-S1 || CYPM1111 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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− | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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− | *'''[LOADER_NAME]''' |
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− | *[LOADER_NAME] |
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− | *[LOADER_NAME] |
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− | |} |
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− | |||
− | ==ECC RAM [OPTIONAL]== |
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− | *Describe ECC RAM restriction here. |
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− | |||
− | ==Vector Table Remap [OPTIONAL]== |
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− | *Describe Vector Table Remap here.. |
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− | |||
− | ==Watchdog Handling== |
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− | *The device does not have a watchdog. |
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− | *The device has a watchdog [WATCHDOGNAME]. |
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− | *The watchdog is fed during flash programming. |
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− | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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− | |||
− | ==Multi-Core Support [OPTIONAL]== |
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− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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− | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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− | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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− | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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− | {| class="seggertable" |
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+ | | PMG1-S2 || CYPM1211 || Internal Flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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− | ! Core || J-Link Support |
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− | | |
+ | | PMG1-S3 || CYPM1311 || Internal Flash || 0x00000000 || 256 KB || style="text-align:center;"| {{YES}} |
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|} |
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+ | ==Watchdog Handling== |
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− | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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+ | *The device has a watchdog WDT. |
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− | ===Main core=== |
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+ | *The watchdog is not fed during flash programming. |
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− | ====Init/Setup==== |
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− | *Initializes the ECC RAM, see [[XXX | XXX]] |
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− | *Enables debugging |
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− | ====Reset==== |
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− | *Device specific reset is performed, see [[XXX | XXX]] |
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− | ====Attach==== |
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− | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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− | ===Secondary core(s)=== |
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− | ====Init/Setup==== |
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− | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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− | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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− | ====Reset==== |
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− | No reset is performed. |
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− | ====Attach==== |
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− | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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+ | The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:<br> |
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+ | * Reset mode: <br> J-Link toggles the XRES line and then sends SWD commands.<br>Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin.<br> |
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+ | * Power Cycle mode:<br> J-Link powers on the target and then starts sending the SWD commands.<br>Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.<br>Make sure to set VSupply (pin 19) correctly before connecting it to the target board.<br>This is the only mode supported by PMG1-S0 devices.<br> |
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+ | A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.<br> |
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+ | |||
===Reset=== |
===Reset=== |
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− | *The device uses |
+ | *The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point. |
− | *The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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− | *The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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− | *The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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− | *The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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− | *The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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− | *The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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− | *The device uses custom reset:..... |
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==Limitations== |
==Limitations== |
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− | ===Dual Core Support=== |
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− | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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− | Attach is not supported |
+ | Attach is not supported because the J-Link resets the device on connect. |
− | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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+ | *[[Infineon_EVAL_PMG1_B1_DRP| EVAL_PMG1_B1_DRP]] |
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− | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
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− | ==Example Application== |
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− | *[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]] |
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− | == |
+ | ==Example Application== |
+ | *[[Infineon_EVAL_PMG1_B1_DRP#Example_Project | EVAL_PMG1_B1_DRP]] |
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− | The following trace example projects are available: |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S0_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S0 Prototyping kit]] |
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− | * [Link to Board Article1] |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S1_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S1 Prototyping kit]] |
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− | * [Link to Board Article2] |
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+ | *[[Infineon_CY7110EZ-PD_PMG1-S2_Prototyping_kit#Example_Project | CY7110EZ-PD PMG1-S2 Prototyping kit]] |
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− | * ... |
Latest revision as of 09:44, 14 May 2024
The Infineon PMG1 is a family of high-voltage USB PD MCUs with Arm® Cortex®-M0/Cortex-M0+ CPU.
Contents
Flash Banks
Internal Flash
Subfamily | Devices | Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|---|---|
PMG1-B1 | CYPM1115/1116 | Internal Flash | 0x00000000 | 128 KB | |
PMG1-S0 | CYPM1011 | Internal Flash | 0x00000000 | 64 KB | |
PMG1-S1 | CYPM1111 | Internal Flash | 0x00000000 | 128 KB | |
PMG1-S2 | CYPM1211 | Internal Flash | 0x00000000 | 128 KB | |
PMG1-S3 | CYPM1311 | Internal Flash | 0x00000000 | 256 KB |
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog is not fed during flash programming.
Device Specific Handling
Connect
The connect sequence of PMG1 devices is very time critical and is performed from the J-Link's side directly in either one of these 2 modes:
- Reset mode:
J-Link toggles the XRES line and then sends SWD commands.
Reset mode is not supported by PMG1-S0 devices because they do not have an XRES pin. - Power Cycle mode:
J-Link powers on the target and then starts sending the SWD commands.
Therefore the target device needs to be supplied via Pin 19 of the J-Link and Pin 1 also needs to be connected to pin 19 of the J-Link.
Make sure to set VSupply (pin 19) correctly before connecting it to the target board.
This is the only mode supported by PMG1-S0 devices.
A device with reconfigured SWD pins runs automatically the acquire sequence to get control of the SWD pins for debugging back.
Reset
- The device uses custom reset via AIRCR.SYSRESETREQ and halt at application entry point.
Limitations
Attach
Attach is not supported because the J-Link resets the device on connect.
Evaluation Boards
- EVAL_PMG1_B1_DRP
- CY7110EZ-PD PMG1-S0 Prototyping kit
- CY7110EZ-PD PMG1-S1 Prototyping kit
- CY7110EZ-PD PMG1-S2 Prototyping kit