Difference between revisions of "Xilinx Zynq UltraScalePlus"
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| + | The '''Xilinx Zynq UltraScale+''' is a multi-processor system on chip, that contains up to 4 ARM Cortex-A53 application processor cores, 2 ARM Cortex-R5 real-time processor cores and user-programmagble logic (FGPA). It can optionally include ARM Mali-400MP2 graphical processor, H.264/H.265 Video Codec, RF and digital front-end subsystem. |
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__TOC__ |
__TOC__ |
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| + | ==Multi-Core Support== |
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| − | This article describes device specifics of the Xilinx Zynq UltraScale+ series devices. |
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| + | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| + | The Zynq UltraScale+ family comes with a variety of multi-core options.<br> |
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| + | The device contains 2 Microblaze cores (CSU and PMU) that implements security and platform management features. These cores are responsible for boot and system configuration processes. |
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| + | {| class="seggertable" |
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| − | = Families = |
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| + | |- |
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| − | The Zynq UltraScale+ series consists of the following families: |
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| + | ! Core || J-Link Support |
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| − | * Zynq UltraScale+ CG (2x Cortex-A53, 2x Cortex-R5) |
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| + | |- |
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| − | * Zynq UltraScale+ DR (4x Cortex-A53, 2x Cortex-R5) |
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| − | + | | 4x Cortex-A53 || style="text-align:center;"| {{YES}} |
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| + | |- |
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| − | * Zynq UltraScale+ EV (4x Cortex-A53, 2x Cortex-R5) |
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| + | | 2x Cortex-R5 || style="text-align:center;"| {{YES}} |
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| − | |||
| + | |- |
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| − | = Debugging the Cortex-R5 = |
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| + | | 1x Microblaze CSU || style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | | 1x Microblaze PMU || style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | | 1x Mali GPU || style="text-align:center;"| {{NO}} |
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| + | |} |
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| + | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| + | ===Cortex-A53=== |
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| + | ====Init/Setup==== |
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| + | In order to connect to and debug one of the available Cortex-A53 on the UltraScale+ series, an UltraScale+ device with ''XCZU..._A53_n'' must be selected. For a list of supported device names, please refer to the [https://www.segger.com/downloads/supported-devices.php list of supported devices] on the SEGGER website. |
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| + | Before releasing the core from reset J-Link loads an "Infinite loop" code at the 0xFFFF0000 address. |
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| + | ====Reset==== |
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| + | When connecting to the Cortex-A53, J-Link will by default reset the core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device. |
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| + | When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset. |
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| + | ====Attach==== |
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| + | Attach is not supported because the J-Link initializes certain RAM regions by default and supports JTAG boot mode only. |
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| + | ===Cortex-R5=== |
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| + | ====Init/Setup==== |
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In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with ''XCZU..._R5_0'' must be selected. For a list of supported device names, please refer to the [https://www.segger.com/downloads/supported-devices.php list of supported devices] on the SEGGER website. |
In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with ''XCZU..._R5_0'' must be selected. For a list of supported device names, please refer to the [https://www.segger.com/downloads/supported-devices.php list of supported devices] on the SEGGER website. |
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| + | ====Reset==== |
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| − | |||
| + | When connecting to the Cortex-R5, J-Link will by default reset the core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device. |
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| − | == Software requirements == |
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| − | J-Link software [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack V6.45c] or later is required. Older versions will not work. |
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| − | |||
| − | == Connect == |
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| − | When connecting to the Cortex-R5, J-Link will by default reset the Cortex-R5 core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device. |
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| − | |||
| − | == Reset == |
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When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset. |
When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset. |
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| + | ====Attach==== |
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| − | |||
| + | Attach is not supported because the J-Link initializes certain RAM regions by default and supports JTAG boot mode only. |
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| − | == Sample project == |
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| + | ==Limitations== |
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| + | J-Link only supports JTAG-boot mode, as ARM DAP access can be enabled externaly. Cortex-A53 and Cortex-R5 are held in reset by default in this mode.<br> |
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| + | JTAG access to the ARM DAP is enabled by J-Link before connecting to the target.<br> |
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| + | J-Link supports only connection via the PS JTAG interface. |
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| + | ==Example Application== |
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| + | ===Cortex-R5 core=== |
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The following example project is for SEGGER Embedded Studio V4.12 and later. It loads a simple Cnt++ loop application into the OCM RAM of the Zynq UltraScale+. |
The following example project is for SEGGER Embedded Studio V4.12 and later. It loads a simple Cnt++ loop application into the OCM RAM of the Zynq UltraScale+. |
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| + | [[File:Xilinx_XCZU3EG_R5_0_CntLoop_ES.zip]] |
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| − | |||
| − | [[File:Xilinx_XCZU3EG_R5_0_CntLoop_ES.zip | Download]] |
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| − | |||
| − | = Debugging the Cortex-A53 = |
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| − | TBD. |
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Latest revision as of 11:46, 24 May 2024
The Xilinx Zynq UltraScale+ is a multi-processor system on chip, that contains up to 4 ARM Cortex-A53 application processor cores, 2 ARM Cortex-R5 real-time processor cores and user-programmagble logic (FGPA). It can optionally include ARM Mali-400MP2 graphical processor, H.264/H.265 Video Codec, RF and digital front-end subsystem.
Contents
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The Zynq UltraScale+ family comes with a variety of multi-core options.
The device contains 2 Microblaze cores (CSU and PMU) that implements security and platform management features. These cores are responsible for boot and system configuration processes.
| Core | J-Link Support |
|---|---|
| 4x Cortex-A53 | 
|
| 2x Cortex-R5 |
|
| 1x Microblaze CSU | 
|
| 1x Microblaze PMU |
|
| 1x Mali GPU |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A53
Init/Setup
In order to connect to and debug one of the available Cortex-A53 on the UltraScale+ series, an UltraScale+ device with XCZU..._A53_n must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website. Before releasing the core from reset J-Link loads an "Infinite loop" code at the 0xFFFF0000 address.
Reset
When connecting to the Cortex-A53, J-Link will by default reset the core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset.
Attach
Attach is not supported because the J-Link initializes certain RAM regions by default and supports JTAG boot mode only.
Cortex-R5
Init/Setup
In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with XCZU..._R5_0 must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website.
Reset
When connecting to the Cortex-R5, J-Link will by default reset the core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.
Attach
Attach is not supported because the J-Link initializes certain RAM regions by default and supports JTAG boot mode only.
Limitations
J-Link only supports JTAG-boot mode, as ARM DAP access can be enabled externaly. Cortex-A53 and Cortex-R5 are held in reset by default in this mode.
JTAG access to the ARM DAP is enabled by J-Link before connecting to the target.
J-Link supports only connection via the PS JTAG interface.
Example Application
Cortex-R5 core
The following example project is for SEGGER Embedded Studio V4.12 and later. It loads a simple Cnt++ loop application into the OCM RAM of the Zynq UltraScale+. File:Xilinx XCZU3EG R5 0 CntLoop ES.zip
