Difference between revisions of "Tracing on Hilscher netX90"
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The Hilscher netX90 MCU implements tracing via pins , so a J-Trace can be used for tracing. |
The Hilscher netX90 MCU implements tracing via pins , so a J-Trace can be used for tracing. |
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| − | = Minimum requirements = |
+ | == Minimum requirements == |
In order to use trace on the Hilscher netX90 MCU devices, the following minimum requirements have to be met: |
In order to use trace on the Hilscher netX90 MCU devices, the following minimum requirements have to be met: |
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| − | * J-Link software version |
+ | * J-Link software version V7.54c or later |
| − | * Ozone |
+ | * Ozone V3.24d or later (if streaming trace and / or the sample project from below shall be used) |
* J-Trace PRO for Cortex-M HW version V1.0 or later |
* J-Trace PRO for Cortex-M HW version V1.0 or later |
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* Tracepin connection like on the NXHX 90-JTAG eval board (See Specifics/Limitations for more information) |
* Tracepin connection like on the NXHX 90-JTAG eval board (See Specifics/Limitations for more information) |
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| + | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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| − | = Sample project = |
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| + | |||
| − | == Streaming trace == |
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| + | == Sample project == |
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| + | === Streaming trace on the COM core === |
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The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a ''NXHX 90-JTAG'' board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a ''NXHX 90-JTAG'' board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
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[[Media:Hilscher_netX90_Trace_Example.zip | Hilscher_netX90_Trace_Example.zip]] |
[[Media:Hilscher_netX90_Trace_Example.zip | Hilscher_netX90_Trace_Example.zip]] |
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| + | === Streaming trace on the APP core === |
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| − | '''Note:''' The example is shipped with a compiled .JLinkScriptfile, should you need the original source it can be requested at [mailto:support@segger.com support@segger.com] |
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| + | The Hilscher netX90 features a second core labelled as the APP core. |
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| + | To be able to connect to this core it first needs to be enabled via an application running in the COM core. Initialization of the APP core is user responsibility. For more information on application setup, FLASH programming and debugging of APP core please refer to [https://hilscher.atlassian.net/wiki/spaces/NETX/pages/144201938/How+to+debug+netX+90+application+side+with+J-Link+debug+probe+from+SEGGER How to debug netX 90 application side with J-Link debug probe from SEGGER?] in the Hilscher Knowledge Base. |
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| + | |||
| + | After the APP core is enabled you can connect to it as described in linked How To. We have tested tracing for the example project provided by Hilscher running from internal FLASH (JLink_PNSV5_simpleConfig_V4.x.x.x). In order to enable tracing in Ozone, please download the example project and add the files contained in following archive: |
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| + | |||
| + | [[Media:JLink_PNSV5_simpleConfig_V4.x.x.x_trace.zip | JLink_PNSV5_simpleConfig_V4.x.x.x_trace.zip]] |
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| + | |||
| + | Now start Ozone using the provided pns_simpleconfig_iflash_trace.jdebug and attach to the running core (Debug->Start Debug Session->Attach & Halt Program). See How To article on details why this is necessary. Tracing will be configured and enabled on next Continue or Step. |
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| + | |||
| + | If everything worked correctly you should now get trace data from the APP core. |
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| − | = Specifics/Limitations = |
+ | == Specifics/Limitations == |
Pin trace on this target device can only be used with SWD, not with JTAG as some JTAG pins are shared with trace pins on this target device. |
Pin trace on this target device can only be used with SWD, not with JTAG as some JTAG pins are shared with trace pins on this target device. |
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On the eval board used for this example the trace pins share functionality with status LEDs. When designing your own trace board we recommend not to share the trace lanes with other functionality to reduce possible signal integrity issues of the high frequency trace signals. |
On the eval board used for this example the trace pins share functionality with status LEDs. When designing your own trace board we recommend not to share the trace lanes with other functionality to reduce possible signal integrity issues of the high frequency trace signals. |
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| − | = Tested Hardware = |
+ | == Tested Hardware == |
[[File:netx90.jpg|none|thumb|NXHX 90-JTAG]] |
[[File:netx90.jpg|none|thumb|NXHX 90-JTAG]] |
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| − | = Reference trace signal quality = |
+ | == Reference trace signal quality == |
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| − | == Trace clock signal quality == |
+ | === Trace clock signal quality === |
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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[[File:netx90_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
[[File:netx90_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
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| − | == Rise time == |
+ | === Rise time === |
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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[[File:netx90_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
[[File:netx90_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
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| − | == Setup time == |
+ | === Setup time === |
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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[[File:netx90_Setuptime_TD0.png|none|thumb|TD0 setup time]] |
[[File:netx90_Setuptime_TD0.png|none|thumb|TD0 setup time]] |
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Latest revision as of 14:09, 6 June 2024
Contents
This article describes how to get started with trace on the Hilscher netX90 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The Hilscher netX90 MCU implements tracing via pins , so a J-Trace can be used for tracing.
Minimum requirements
In order to use trace on the Hilscher netX90 MCU devices, the following minimum requirements have to be met:
- J-Link software version V7.54c or later
- Ozone V3.24d or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later
- Tracepin connection like on the NXHX 90-JTAG eval board (See Specifics/Limitations for more information)
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Sample project
Streaming trace on the COM core
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a NXHX 90-JTAG board. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Hilscher_netX90_Trace_Example.zip
Streaming trace on the APP core
The Hilscher netX90 features a second core labelled as the APP core. To be able to connect to this core it first needs to be enabled via an application running in the COM core. Initialization of the APP core is user responsibility. For more information on application setup, FLASH programming and debugging of APP core please refer to How to debug netX 90 application side with J-Link debug probe from SEGGER? in the Hilscher Knowledge Base.
After the APP core is enabled you can connect to it as described in linked How To. We have tested tracing for the example project provided by Hilscher running from internal FLASH (JLink_PNSV5_simpleConfig_V4.x.x.x). In order to enable tracing in Ozone, please download the example project and add the files contained in following archive:
JLink_PNSV5_simpleConfig_V4.x.x.x_trace.zip
Now start Ozone using the provided pns_simpleconfig_iflash_trace.jdebug and attach to the running core (Debug->Start Debug Session->Attach & Halt Program). See How To article on details why this is necessary. Tracing will be configured and enabled on next Continue or Step.
If everything worked correctly you should now get trace data from the APP core.
Specifics/Limitations
Pin trace on this target device can only be used with SWD, not with JTAG as some JTAG pins are shared with trace pins on this target device.
On the eval board used for this example the trace pins share functionality with status LEDs. When designing your own trace board we recommend not to share the trace lanes with other functionality to reduce possible signal integrity issues of the high frequency trace signals.
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
